S3C2440A Samsung, S3C2440A Datasheet

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S3C2440A

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S3C2440A
Description
Manufacturer
Samsung
Datasheet

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S3C2440A
32-BIT CMOS
MICROCONTROLLER
USER'S MANUAL
Revision 1

Related parts for S3C2440A

S3C2440A Summary of contents

Page 1

... S3C2440A 32-BIT CMOS MICROCONTROLLER USER'S MANUAL Revision 1 ...

Page 2

... S3C2440A 32-Bit CMOS Microcontroller User's Manual, Revision 1 Publication Number: 21-S3-C2440A-072004 © 2004 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics ...

Page 3

... Chapter 1 Product Overview Introduction.........................................................................................................................................1-1 Features .............................................................................................................................................1-2 Block Diagram ....................................................................................................................................1-5 Pin Assignments.................................................................................................................................1-6 Signal Descriptions..............................................................................................................................1-20 S3C2440A Special Registers................................................................................................................1-26 Chapter 2 Programmer's Model Overview .............................................................................................................................................2-1 Processor Operating States .........................................................................................................2-1 Switching State...........................................................................................................................2-1 Memory Formats.........................................................................................................................2-1 Big-Endian Format.......................................................................................................................2-2 Little-Endian Format ....................................................................................................................2-2 Instruction Length........................................................................................................................2-2 Operating Modes .........................................................................................................................2-3 Registers ....................................................................................................................................2-3 The Program Status Registers ......................................................................................................2-7 Exceptions .................................................................................................................................2-10 Interrupt Latencies .......................................................................................................................2-15 Reset ...

Page 4

... Reserved Bits..............................................................................................................................3-20 Examples ...................................................................................................................................3-20 Instruction Cycle Times................................................................................................................3-20 Assembly Syntax ........................................................................................................................3-21 Examples ...................................................................................................................................3-21 Multiply And Multiply-Accumulate (MUL, MLA).......................................................................................3-22 Cpsr Flags ..................................................................................................................................3-24 Instruction Cycle Times................................................................................................................3-24 Assembler Syntax .......................................................................................................................3-24 Examples ...................................................................................................................................3-24 Multiply Long And Multiply-Accumulate Long (MULL, MLAL) ...................................................................3-25 Operand Restrictions ...................................................................................................................3-26 Cpsr Flags ..................................................................................................................................3-26 Instruction Cycle Times................................................................................................................3-26 Assembler Syntax .......................................................................................................................3-27 Examples ...................................................................................................................................3-27 iv (Continued) S3C2440A MICROCONTROLLER ...

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... Single Data Swap (SWP).....................................................................................................................3-47 Bytes and Words ........................................................................................................................3-47 Use of R15..................................................................................................................................3-48 Data Aborts ................................................................................................................................3-48 Instruction Cycle Times................................................................................................................3-48 Assembler Syntax .......................................................................................................................3-48 Software Interrupt (SWI) .......................................................................................................................3-49 Return from the Supervisor ...........................................................................................................3-49 Comment Field............................................................................................................................3-49 Instruction Cycle Times................................................................................................................3-49 Assembler Syntax .......................................................................................................................3-50 Coprocessor Data Operations (CDP).....................................................................................................3-51 Coprocessor Instructions..............................................................................................................3-51 Instruction Cycle Times................................................................................................................3-52 Examples ...................................................................................................................................3-52 S3C2440A MICROCONTROLLER (Continued) (Continued) v ...

Page 6

... Loading a Word from an Unknown Alignment .................................................................................3-63 Chapter 4 Thumb Instruction Set Thumb Instruction Set Format...............................................................................................................4-1 Format Summary ........................................................................................................................4-2 Opcode Summary .......................................................................................................................4-3 Format 1: Move Shifted Register ...........................................................................................................4-5 Operation....................................................................................................................................4-5 Instruction Cycle Times................................................................................................................4-6 Examples ...................................................................................................................................4-6 Format 2: Add/Subtract........................................................................................................................4-7 Operation....................................................................................................................................4-7 Instruction Cycle Times................................................................................................................4-8 Examples ...................................................................................................................................4-8 Format 3: Move/Compare/Add/Subtract Immediate.................................................................................4-9 Operations ..................................................................................................................................4-9 Instruction Cycle Times................................................................................................................4-10 Examples ...................................................................................................................................4-10 vi (Continued) (Continued) S3C2440A MICROCONTROLLER ...

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... Operation....................................................................................................................................4-23 Instruction Cycle Times................................................................................................................4-23 Examples ...................................................................................................................................4-23 Format 10: Load/Store Halfword............................................................................................................4-24 Operation....................................................................................................................................4-24 Examples ...................................................................................................................................4-25 Format 11: SP-Relative Load/Store .......................................................................................................4-26 Operation....................................................................................................................................4-26 Instruction Cycle Times................................................................................................................4-27 Examples ...................................................................................................................................4-27 Format 12: Load Address.....................................................................................................................4-28 Operation....................................................................................................................................4-28 Instruction Cycle Times................................................................................................................4-29 Examples ...................................................................................................................................4-29 Format 13: Add Offset to Stack Pointer .................................................................................................4-30 Operation....................................................................................................................................4-30 Instruction Cycle Times................................................................................................................4-30 Examples ...................................................................................................................................4-30 S3C2440A MICROCONTROLLER (Continued) (Continued) vii ...

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... Instruction Cycle Times................................................................................................................4-36 Examples ...................................................................................................................................4-36 Format 18: Unconditional Branch..........................................................................................................4-37 Operation....................................................................................................................................4-37 Examples ...................................................................................................................................4-37 Format 19: long branch with link ...........................................................................................................4-38 Operation....................................................................................................................................4-38 Instruction Cycle Times................................................................................................................4-39 Examples ...................................................................................................................................4-39 Instruction Set Examples .....................................................................................................................4-40 Multiplication by A Constant Using Shifts and Adds........................................................................4-40 General Purpose Signed Divide.....................................................................................................4-41 Division by a Constant .................................................................................................................4-43 viii (Continued) (Continued) S3C2440A MICROCONTROLLER ...

Page 9

... Nand Flash Configuration Register ................................................................................................6-12 Control Register ..........................................................................................................................6-13 Command Register......................................................................................................................6-15 Address Register.........................................................................................................................6-15 Data Register..............................................................................................................................6-15 Main Data Area Register ..............................................................................................................6-16 Spare Area Ecc Register.............................................................................................................6-17 NFCON Status Register...............................................................................................................6-18 ECC0/1 Status Register...............................................................................................................6-19 Main Data Area ECC0 Status Register ..........................................................................................6-20 Spare Area ECC Status Register ..................................................................................................6-20 Block Address Register ...............................................................................................................6-21 S3C2440A MICROCONTROLLER (Continued) ix ...

Page 10

... DMA Initial Source Control (DISRCC) Register ...............................................................................8-7 DMA Initial Destination (DIDST) Register .......................................................................................8-8 DMA Initial Destination Control (DIDSTC) Register..........................................................................8-8 DMA Control (DCON) Register......................................................................................................8-9 DMA Status (DSTAT) Register......................................................................................................8-12 DMA Current Source (DCSRC) Register ........................................................................................8-13 Current Destination (DCDST) Register ...........................................................................................8-13 DMA Mask Trigger (DMASKTRIG) Register....................................................................................8-14 x (Continued) S3C2440A MICROCONTROLLER ...

Page 11

... DCLK Control Registers (DCLKCON).............................................................................................9-25 EXTINTn (External Interrupt Control Register n)...............................................................................9-26 EINTFLTn (External Interrupt Filter Register n)................................................................................9-30 EINTMASK (External Interrupt Mask Register) ...............................................................................9-31 EINTPEND (External Interrupt Pending Register) ............................................................................9-32 GSTATUSn (General Status Registers) .........................................................................................9-33 DSCn (Drive Strength Control).......................................................................................................9-34 DSCn (Drive Strength Control).......................................................................................................9-35 MSLCON (Memory Sleep Control Register)....................................................................................9-36 S3C2440A MICROCONTROLLER (Continued) xi ...

Page 12

... Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2/TCMPB2)...................................10-17 Timer 2 Count Observation Register (TCNTO2) ...............................................................................10-17 Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3/TCMPB3)...................................10-18 Timer 3 Count Observation Register (TCNTO3) ...............................................................................10-18 Timer 4 Count Buffer Register (TCNTB4) ........................................................................................10-19 Timer 4 Count Observation Register (TCNTO4) ...............................................................................10-19 xii Table of Contents (Continued) S3C2440A MICROCONTROLLER ...

Page 13

... Uart Transmit Buffer Register (HOLDING Register & FIFO Register) .................................................11-20 Uart Receive Buffer Register (HOLDING Register & FIFO Register) ..................................................11-20 Uart Baud Rate Divisor Register....................................................................................................11-21 Chapter 12 USB HOST Controller Overview .............................................................................................................................................12-1 Usb Host Controller Special Registers ...................................................................................................12-2 OHCI Registers for Usb Host Controller .........................................................................................12-2 S3C2440A MICROCONTROLLER (Continued) xiii ...

Page 14

... Interrupt Controller Special Registers.....................................................................................................14-7 Source Pending (SRCPND) Register .............................................................................................14-7 Interrupt Mode (INTMOD) Register.................................................................................................14-9 Interrupt Mask (INTMSK) Register.................................................................................................14-11 Priority Register (PRIORITY).........................................................................................................14-13 Interrupt Pending (INTPND) Register..............................................................................................14-14 Interrupt Offset (INTOFFSET) Register...........................................................................................14-16 Sub Source Pending (SUBSRCPND) Register................................................................................14-17 Interrupt Sub Mask (INTSUBMSK) Register ...................................................................................14-18 xiv (Continued) S3C2440A MICROCONTROLLER ...

Page 15

... ADC AND Touch Screen Interface Special Registers ..............................................................................16-5 ADC Control Register (ADCCON)..................................................................................................16-5 ADC Touch Screen Control Register (ADCTSC)..............................................................................16-6 ADC Start Delay Register (ADCDLY).............................................................................................16-7 ADC Conversion Data Register (ADCDAT0)....................................................................................16-8 ADC Conversion Data Register (ADCDAT1)....................................................................................16-9 ADC Touch Screen Up-Down INT Check Register (ADCUPDN) ........................................................16-9 S3C2440A MICROCONTROLLER (Continued) xv ...

Page 16

... BCD Year (BCDYEAR) Register ...................................................................................................17-10 Chapter 18 Watchdog Timer Overview .............................................................................................................................................18-1 Features .....................................................................................................................................18-1 Watchdog Timer Operation...........................................................................................................18-2 Wtdat & Wtcnt ............................................................................................................................18-2 Consideration of Debugging Environment .......................................................................................18-2 Watchdog Timer Special Registers .......................................................................................................18-3 Watchdog Timer Control (WTCON) Register...................................................................................18-3 Watchdog Timer Data (WTDAT) Register.......................................................................................18-4 Watchdog Timer Count (WTCNT) Register .....................................................................................18-4 xvi (Continued) S3C2440A MICROCONTROLLER ...

Page 17

... Configuring IIC-Bus ......................................................................................................................20-6 Flowcharts of Operations in Each Mode.........................................................................................20-7 IIC-Bus Interface Special Registers .......................................................................................................20-11 Multi-Master IIC-Bus Control (IICCON) Register ..............................................................................20-11 Multi-Master IIC-Bus Control/Status (IICSTAT) Register...................................................................20-12 Multi-Master IIC-Bus Address (IICADD) Register.............................................................................20-13 Multi-Master IIC-Bus Transmit/Receive Data Shift (IICDS) Register...................................................20-13 Multi-Master IIC-Bus Line Contro l(IICLC) Register ..........................................................................20-14 S3C2440A MICROCONTROLLER (Continued) xvii ...

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... Programming Procedure...............................................................................................................22-3 SPI Transfer Format.....................................................................................................................22-4 Transmitting Procedure for DMA ...................................................................................................22-5 Receiving Procedure for DMA .......................................................................................................22-5 SPI Special Registers ..........................................................................................................................22-6 SPI Control Register ....................................................................................................................22-6 SPI Status Register.....................................................................................................................22-7 SPI Pin Control Register ..............................................................................................................22-8 SPI Baud Rate Prescaler Register ................................................................................................22-9 SPI Tx Data Register ...................................................................................................................22-9 SPI Rx Data Register...................................................................................................................22-9 xviii (Continued) S3C2440A MICROCONTROLLER ...

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... Codec Pre-Scaler Control Register 2.............................................................................................23-21 Codec Main-Scaler Control Register..............................................................................................23-22 Codec Dma Target Area Register..................................................................................................23-22 Codec Status Register.................................................................................................................23-23 RGB1 Start Address Register.......................................................................................................23-23 RGB2 Start Address Register.......................................................................................................23-23 RGB3 Start Address Register.......................................................................................................23-24 RGB4 Start Address Register.......................................................................................................23-24 Preview Target Format Register ....................................................................................................23-24 Preview DMA Control Register ......................................................................................................23-25 S3C2440A MICROCONTROLLER (Continued) xix ...

Page 20

... AC97 Codec Command Register (AC_CODEC_CMD).....................................................................24-10 AC97 Codec Status Register (AC_CODEC_STAT) .........................................................................24-11 AC97 PCM Out/In Channel FIFO Address Register (AC_PCMADDR) ...............................................24-11 AC97 MIC in Channel FIFO Address Register (AC_MICADDR) ........................................................24-12 AC97 PCM Out/In Channel FIFO Data Register (AC_PCMDATA).....................................................24-12 AC97 MIC in Channel FIFO Data Register (AC_MICDATA)..............................................................24-12 xx (Continued) (Continued) S3C2440A MICROCONTROLLER ...

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... Table of Contents Chapter 25 Bus Priorities Overview .............................................................................................................................................25-1 Bus Priority Map .........................................................................................................................25-1 Chapter 26 Mechanical Data Package Dimensions ...........................................................................................................................26-1 Chapter 27 Electrical Data Absolute Maximum Ratings..................................................................................................................27-1 Recommended Operating Conditions.....................................................................................................27-2 D.C. Electrical Characteristics..............................................................................................................27-3 A.C. Electrical Characteristics..............................................................................................................27-8 S3C2440A MICROCONTROLLER (Continued) xxi ...

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... Figure Number 1-1 S3C2440A Block Diagram................................................................................................1-5 1-2 S3C2440A Pin Assignments (289-FBGA)..........................................................................1-6 2-1 Big-Endian Addresses of Bytes within Words.....................................................................2-2 2-2 Little-Endian Addresses of Bytes within Words ..................................................................2-2 2-3 Register Organization in ARM State..................................................................................2-4 2-4 Register Organization in THUMB state ..............................................................................2-5 2-5 Mapping of THUMB State Registers onto ARM State Registers ...........................................2-6 2-6 Program Status Register Format.......................................................................................2-7 3-1 ARM Instruction Set Format .............................................................................................3-1 3-2 Branch and Exchange Instructions ...

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... Format 16.......................................................................................................................4-34 4-18 Format 17.......................................................................................................................4-36 4-19 Format 18.......................................................................................................................4-37 4-20 Format 19.......................................................................................................................4-38 5-1 S3C2440A Memory Map after Reset .................................................................................5-2 5-2 S3C2440A External nWAIT Timing Diagram (Tacc=4) .........................................................5-6 5-3 S3C2440A nXBREQ/nXBACK Timing Diagram ...................................................................5-7 5-4 Memory Interface with 8-bit ROM ......................................................................................5-8 5-5 Memory Interface with 8-bit ROM x 2.................................................................................5-8 5-6 Memory Interface with 8-bit ROM x 4.................................................................................5-9 5-7 Memory Interface with 16-bit ROM ....................................................................................5-9 5-8 Memory Interface with 16-bit SRAM ...

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... Whole service in Handshake Mode with Unit Transfer Size..................................................8-6 10-1 16-bit PWM Timer Block Diagram .....................................................................................10-2 10-2 Timer Operations .............................................................................................................10-3 10-3 Example of Double Buffering Function ...............................................................................10-4 10-4 Example of a Timer Operation...........................................................................................10-6 10-5 Example of PWM............................................................................................................10-7 10-6 Inverter On/Off .................................................................................................................10-8 10-7 The Wave Form When a Dead Zone Feature is Enabled......................................................10-9 10-8 Timer4 DMA Mode Operation............................................................................................10-10 S3C2440A MICROCONTROLLER List of Figures (Continued) Title Page Number xxv ...

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... IIC-Bus Block Diagram.....................................................................................................20-2 20-2 Start and Stop Condition ..................................................................................................20-3 20-3 IIC-Bus Interface Data Format ...........................................................................................20-4 20-4 Data Transfer on the IIC-Bus .............................................................................................20-5 20-5 Acknowledge on the IIC-Bus .............................................................................................20-5 20-6 Operations for Master/Transmitter Mode ............................................................................20-7 20-7 Operations for Master/Receiver Mode ................................................................................20-8 20-8 Operations for Slave/Transmitter Mode ..............................................................................20-9 20-9 Operations for Slave/Receiver Mode ..................................................................................20-10 xxvi List of Figures (Continued) Title Page Number S3C2440A MICROCONTROLLER ...

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... Power-On Oscillation Setting Timing Diagram ....................................................................27-10 27-8 Sleep Mode Return Oscillation Setting Timing Diagram.......................................................27-11 27-9 ROM/SRAM Burst READ Timing Diagram (I) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=0, DW=16bit)...............................27-12 27-10 ROM/SRAM Burst READ Timing Diagram (II) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=1, DW=16bit)...............................27-13 S3C2440A MICROCONTROLLER List of Figures (Continued) Title Page Number xxvii ...

Page 27

... TFT LCD Controller Timing Diagram...................................................................................27-31 27-32 IIS Interface Timing Diagram .............................................................................................27-32 27-33 IIC Interface Timing Diagram .............................................................................................27-32 27-34 SD/MMC Interface Timing Diagram....................................................................................27-33 27-35 SPI Interface Timing Diagram (CPHA=1, CPOL=1) .............................................................27-33 27-36 NAND Flash Address/Command Timing Diagram ...............................................................27-34 27-37 NAND Flash Timing Diagram ............................................................................................27-34 xxviii List of Figures (Continued) Title Page Number S3C2440A MICROCONTROLLER ...

Page 28

... Table Number 1-1 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 1 of 3).....................................1-7 1-2 S3C2440A 289-Pin FBGA Pin Assignments (Sheet 1 of 9)..................................................1-10 1-3 S3C2440A Signal Descriptions (Sheet 1 of 6).....................................................................1-20 1-4 S3C2440A Special Registers (Sheet 1 of 14) .....................................................................1-26 2-1 PSR Mode Bit Values ......................................................................................................2-9 2-2 Exception Entry/Exit........................................................................................................2-11 2-3 Exception Vectors ...........................................................................................................2-13 3-1 The ARM Instruction Set ..................................................................................................3-2 3-2 Condition Code Summary ...

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... Table Number 8-1 DMA Request Sources for Each Channel...........................................................................8-2 9-1 S3C2440A Port Configuration (Sheet 1 of 5).......................................................................9-2 11-1 Interrupts in Connection with FIFO ...................................................................................11-5 15-1 Relation Between VCLK and CLKVAL (STN, HCLK = 60MHz).............................................15-5 15-2 Dither Duty Cycle Examples.............................................................................................15-7 15-3 Relation between VCLK and CLKVAL (TFT, HCLK = 60MHz) ..............................................15-16 15-4 5:6:5 Format ...................................................................................................................15-21 15-5 5:5:5:1 Format ................................................................................................................15-21 15-6 MV Value for Each Display Mode......................................................................................15-41 21-1 CODEC clock (CODECLK = 256 or 384fs) ...

Page 30

... To reduce total system cost, the S3C2440A includes the following components. The S3C2440A is developed with ARM920T core, 0.13um CMOS standard cells and a memory complier. Its low- power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA) ...

Page 31

... Supports self-refresh mode in SDRAM for power- down. Supports various types of ROM for booting (NOR/NAND Flash, EEPROM, and others). 1-2 S3C2440A RISC MICROPROCESSOR NAND Flash Boot Loader Supports booting from NAND flash memory. 4KB internal buffer for booting. Supports storage memory for NAND flash memory after booting ...

Page 32

... S3C2440A RISC MICROPROCESSOR FEATURES (Continued) Interrupt Controller 60 Interrupt sources (One Watch dog timer, 5 timers, 9 UARTs, 24 external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1 NAND and 2 Camera), 1 AC97 Level/Edge mode on external interrupt source Programmable polarity of edge and level ...

Page 33

... Compatible with USB Specification version 1.1 SD Host Interface Normal, Interrupt and DMA data transfer mode (byte, halfword, word transfer) 1-4 S3C2440A RISC MICROPROCESSOR DMA burst4 access support (only word transfer) Compatible with SD Memory Card Protocol version 1.0 Compatible with SDIO Card Protocol version 1.0 64 Bytes FIFO for Tx/Rx Compatible with Multimedia Card Protocol version 2 ...

Page 34

... Bridge & DMA (4Ch) UART USB Device A SDI/MMC P B Watchdog B Timer U S BUS CONT. Arbitor/Decode SPI 0, 1 SPI Figure 1-1. S3C2440A Block Diagram PRODUCT OVERVIEW External Coproc Interface AMBA Bus I/F Write Buffer WriteBack WBPA[31:0] PA Tag RAM BUS CONT. Arbitor/Decode Interrupt CONT. ...

Page 35

... PRODUCT OVERVIEW PIN ASSIGNMENTS Figure 1-2. S3C2440A Pin Assignments (289-FBGA) 1 S3C2440A RISC MICROPROCESSOR BOTTOM VIEW ...

Page 36

... S3C2440A RISC MICROPROCESSOR Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet Pin Pin Name Number A1 VDDi A2 SCKE A3 VSSi A4 VSSi A5 VSSMOP A6 VDDi A7 VSSMOP A8 ADDR10 A9 VDDMOP A10 VDDi A11 VSSMOP A12 VSSi A13 DATA3 A14 DATA7 A15 VSSMOP A16 VDDi ...

Page 37

... K6 nXDREQ0/GPB10 K7 nXDACK1/GPB7 K8 SDCMD/GPE6 K9 SPIMISO0/GPE11 K10 EINT13/SPIMISO1/GPG5 K11 nCTS0/GPH0 K12 VDDOP K13 TXD0/GPH2 K14 RXD0/GPH3 K15 UEXTCLK/GPH8 K16 TXD1/GPH4 K17 RXD1/GPH5 S3C2440A RISC MICROPROCESSOR Pin Pin Name Number L1 LEND/GPC0 L2 VDDiarm L3 nXDACK0/GPB9 L4 VCLK/GPC1 L5 nXBREQ/GPB6 L6 VD1/GPC9 L7 VFRAME/GPC3 L8 I2SSDI/AC_SDATA_IN L9 SPICLK0/GPE13 L10 EINT15/SPICLK1/GPG7 L11 EINT22/GPG14 ...

Page 38

... S3C2440A RISC MICROPROCESSOR Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet (Continued) Pin Pin Name Number N1 VSSOP N2 VD0/GPC8 N3 VD4/GPC12 N4 VD2/GPC10 N5 VD10/GPD2 N6 VD15/GPD7 N7 VD22/nSS1/GPD14 N8 SDCLK/GPE5 N9 EINT8/GPG0 N10 EINT18/nCTS1/GPG10 N11 DP0 N12 DN1/PDN0 N13 nRSTOUT/GPA21 N14 MPLLCAP N15 VDD_RTC N16 ...

Page 39

... PRODUCT OVERVIEW Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet Pin Pin Number Name F7 ADDR0/GPA0 E7 ADDR1 B7 ADDR2 F8 ADDR3 C7 ADDR4 D8 ADDR5 E8 ADDR6 D7 ADDR7 G8 ADDR8 B8 ADDR9 A8 ADDR10 C8 ADDR11 B9 ADDR12 H8 ADDR13 E9 ADDR14 C9 ADDR15 D9 ADDR16/GPA1 G9 ADDR17/GPA2 F9 ADDR18/GPA3 H9 ADDR19/GPA4 D10 ADDR20/GPA5 C10 ADDR21/GPA6 H10 ADDR22/GPA7 E10 ...

Page 40

... S3C2440A RISC MICROPROCESSOR Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet (Continued) Pin Pin Number Name P16 XP/AIN7 H6 CAMDATA0/GPJ0 G3 CAMDATA1/GPJ1 H5 CAMDATA2/GPJ2 H4 CAMDATA3/GPJ3 H3 CAMDATA4/GPJ4 H7 CAMDATA5/GPJ5 J8 CAMDATA6/GPJ6 H2 CAMDATA7/GPJ7 G5 CAMPCLK/GPJ8 G7 CAMVSYNC/GPJ9 G2 CAMHREF/GPJ10 J3 CAMCLKOUT/GPJ11 J4 CAMRESET/GPJ12 D12 DATA0 C12 DATA1 E11 DATA2 A13 DATA3 F10 DATA4 ...

Page 41

... PRODUCT OVERVIEW Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet (Continued) Pin Pin Number Name E13 DATA19 E12 DATA20 E16 DATA21 F15 DATA22 G13 DATA23 E17 DATA24 G12 DATA25 F14 DATA26 F12 DATA27 G11 DATA28 G16 DATA29 H13 DATA30 F13 DATA31 ...

Page 42

... S3C2440A RISC MICROPROCESSOR Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet (Continued) Pin Pin Number Name T10 EINT16/GPG8 M11 EINT17/nRTS1/GPG9 N10 EINT18/nCTS1/GPG10 U12 EINT19/TCLK1/GPG11 M10 EINT20/GPG12 T11 EINT21/GPG13 L11 EINT22/GPG14 U13 EINT23/GPG15 H12 EXTCLK P17 UPLLCAP N14 MPLLCAP H14 nBATT_FLT D4 nBE0 ...

Page 43

... PRODUCT OVERVIEW Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet (Continued) Pin Pin Number Name E3 nGCS7 D6 nSCAS C6 nSRAS H15 nTRST E4 nWAIT E6 nWE J6 TOUT0/GPB0 J5 TOUT1/GPB1 J7 TOUT2/GPB2 K3 TOUT3/GPB3 K4 TCLK0/GPB4 K2 nXBACK/GPB5 L5 nXBREQ/GPB6 K7 nXDACK1/GPB7 K5 nXDREQ1/GPB8 L3 nXDACK0/GPB9 K6 nXDREQ0/GPB10 T15 OM0 R13 OM1 P13 OM2 T13 OM3 ...

Page 44

... S3C2440A RISC MICROPROCESSOR Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet (Continued) Pin Pin Number Name A2 SCKE B4 SCLK0 B3 SCLK1 P7 I2SLRCK/AC_SYNC R7 I2SSCLK/AC_BIT_CLK T7 CDCLK/AC_nRESET L8 I2SSDI/AC_SDATA_IN U6 I2SSDO/AC_SDATA_OUT N8 SDCLK/GPE5 K8 SDCMD/GPE6 R8 SDDAT0/GPE7 M8 SDDAT1/GPE8 P8 SDDAT2/GPE9 J9 SDDAT3/GPE10 K9 SPIMISO0/GPE11 P9 SPIMOSI0/GPE12 L9 SPICLK0/GPE13 U8 IICSCL/GPE14 M9 IICSDA/GPE15 J13 TCK H17 TDI J16 TDO ...

Page 45

... PRODUCT OVERVIEW Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet (Continued) Pin Pin Number Name N4 VD2/GPC10 R1 VD3/GPC11 N3 VD4/GPC12 P2 VD5/GPC13 M6 VD6/GPC14 P3 VD7/GPC15 R2 VD8/GPD0 M5 VD9/GPD1 N5 VD10/GPD2 R3 VD11/GPD3 P4 VD12/GPD4 R4 VD13/ GPD5 P5 VD14/GPD6 N6 VD15/GPD7 M7 VD16/SPIMISO1/GPD8 T4 VD17/SPIMOSI1/GPD9 R5 VD18/SPICLK1/GPD10 T5 VD19//GPD11 P6 VD20/ GPD12 R6 VD21/ GPD13 N7 VD22/nSS1/GPD14 U5 VD23/nSS0/GPD15 ...

Page 46

... S3C2440A RISC MICROPROCESSOR Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet (Continued) Pin Pin Number Name A1 VDDi A10 VDDi A16 VDDi A6 VDDi B11 VDDi F1 VDDi F16 VDDi U11 VDDi L2 VDDiarm T6 VDDiarm T8 VDDiarm U1 VDDiarm J2 VDDiarm U2 VDDiarm A9 VDDMOP B12 VDDMOP B14 VDDMOP B16 ...

Page 47

... PRODUCT OVERVIEW Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet (Continued) Pin Pin Number Name F2 VSSi G17 VSSi H1 VSSiarm K1 VSSiarm T1 VSSiarm T2 VSSiarm U10 VSSiarm U4 VSSiarm U7 VSSiarm A11 VSSMOP A15 VSSMOP A5 VSSMOP A7 VSSMOP B1 VSSMOP B13 VSSMOP D16 VSSMOP D17 VSSMOP E2 VSSMOP G1 VSSOP ...

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... S3C2440A RISC MICROPROCESSOR The table below shows I/O types and descriptions. Input (I)/Output (O) Type d12i(vdd12ih) d12c(vdd12ih_core), si(vssih) d33o(vdd33oph), so(vssoph) d33th(vdd33th_abb),sth(vssbbh_abb) d12t(vdd12t_abb), st(vssbb_abb) drtc(vdd30th_rtc) t8(phbsu100ct8sm) is(phis) us(pbusb0) t10(phtot10cd) ot(phot8) b8(phob8) t16(phot16sm) r10(phiar10_abb) ia(phia_abb) gp(phgpad_option) m26(phsoscm26_2440a) t12(phbsu100ct12sm) d8(phbsd8sm) t10s(phtot10cd_10_2440a) b12s(phtbsu100ct12cd_12_2440a) d2s(phtbsd2_2440a) r50(phoar50_abb) t12s(phtot12cd_12_2440a) ...

Page 49

... O NCON I FRnB I 1-20 OM[1:0] sets S3C2440A in the TEST mode, which is used only at fabrication. Also, it determines the bus width of nGCS0. The pull-up/down resistor determines the logic level during RESET cycle. 00: Nand-boot 01: 16-bit ADDR[26:0] (Address Bus) outputs the memory address of the corresponding bank . ...

Page 50

... S3C2440A RISC MICROPROCESSOR Table 1-3. S3C2440A Signal Descriptions (Sheet (Continued) Signal Input/ Output LCD Control Unit VD[23:0] O LCD_PWREN O VCLK O VFRAME O VLINE VSYNC O HSYNC O VDEN O LEND O STV O CPV O LCD_HCLK STH O LCD_LPCOE O LCD_LPCREV O LCD_LPCREVB O CAMERA Interface CAMRESET O CAMCLKOUT O CAMPCLK I CAMHREF I CAMVSYNC I CAMDATA[7:0] ...

Page 51

... PRODUCT OVERVIEW Table 1-3. S3C2440A Signal Descriptions (Sheet (Continued) Signal Input/Output UART RxD[2:0] I TxD[2:0] O nCTS[1:0] I nRTS[1:0] O UEXTCLK I ADC AIN[7:0] AI Vref AI IIC-Bus IICSDA IO IICSCL IO IIS-Bus I2SLRCK IO I2SSDO O I2SSDI I I2SSCLK IO CDCLK O AC’97 AC_SYNC AC_BIT_CLK IO AC_nRESET O AC_SDATA_IN I AC_SDATA_OUT O Touch Screen nXPON O XMON O nYPON ...

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... S3C2440A RISC MICROPROCESSOR Table 1-3. S3C2440A Signal Descriptions (Sheet (Continued) Signal Input/Output SPI SPIMISO[1:0] IO SPIMOSI[1:0] IO SPICLK[1:0] IO nSS[1: SDDAT[3:0] IO SDCMD IO SDCLK O General Port GPn[129:0] IO TIMMER/PWM TOUT[3:0] O TCLK[1:0] I JTAG TEST LOGIC nTRST I TMS I TCK I TDI I TDO O SPIMISO is the master data input line, when SPI is configured as a master. ...

Page 53

... Clock output signal. The CLKSEL of MISCCR register configures the clock output mode among the MPLL CLK, UPLL CLK, FCLK, HCLK, PCLK. nRESET suspends any operation in progress and places S3C2440A into a known reset state. For a reset, nRESET must be held to L level for at least 4 OSCin after the processor power has been stabilized. For external device reset control (nRSTOUT = nRESET & ...

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... S3C2440A RISC MICROPROCESSOR Table 1-3. S3C2440A Signal Descriptions (Sheet (Continued) Signal Input/Output Power VDDalive P VDDiarm P VDDi P VSSi/VSSiarm P VDDi_MPLL P VSSi_MPLL P VDDOP P VDDMOP P VSSOP P RTCVDD P VDDi_UPLL P VSSi_UPLL P VDDA_ADC P VSSA_ADC P NOTES: 1. I/O means Input/Output. 2. AI/AO means analog input/analog output means schmitt-trigger means power. Description S3C2440A reset block and port status register V It should be always supplied whether in normal mode or in Sleep mode ...

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... PRODUCT OVERVIEW S3C2440A SPECIAL REGISTERS Table 1-4. S3C2440A Special Registers (Sheet 1 of 14) Register Address Name (B. Endian) Memory Controllers BWSCON 0x48000000 BANKCON0 0x48000004 BANKCON1 0x48000008 BANKCON2 0x4800000C BANKCON3 0x48000010 BANKCON4 0x48000014 BANKCON5 0x48000018 BANKCON6 0x4800001C BANKCON7 0x48000020 REFRESH 0x48000024 BANKSIZE 0x48000028 MRSRB6 0x4800002C ...

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... S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 2 of 14) (Continued) Register Name Address (B. Endian) USB Host Controller HcRevision 0x49000000 HcControl 0x49000004 HcCommonStatus 0x49000008 HcInterruptStatus 0x4900000C HcInterruptEnable 0x49000010 HcInterruptDisable 0x49000014 HcHCCA 0x49000018 HcPeriodCuttentED 0x4900001C HcControlHeadED 0x49000020 HcControlCurrentED 0x49000024 HcBulkHeadED 0x49000028 HcBulkCurrentED 0x4900002C ...

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... PRODUCT OVERVIEW Table 1-4. S3C2440A Special Registers (Sheet 3 of 14) (Continued) Register Address Name (B. Endian) DMA DISRC0 0x4B000000 DISRCC0 0x4B000004 DIDST0 0x4B000008 DIDSTC0 0x4B00000C DCON0 0x4B000010 DSTAT0 0x4B000014 DCSRC0 0x4B000018 DCDST0 0x4B00001C DMASKTRIG0 0x4B000020 DISRC1 0x4B000040 DISRCC1 0x4B000044 DIDST1 0x4B000048 DIDSTC1 0x4B00004C DCON1 ...

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... S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 4 of 14) (Continued) Register Address Name (B. Endian) Clock & Power Management LOCKTIME 0x4C000000 MPLLCON 0x4C000004 UPLLCON 0x4C000008 CLKCON 0x4C00000C CLKSLOW 0x4C000010 CLKDIVN 0x4C000014 CAMDIVN 0x4C000018 LCD Controller LCDCON1 0X4D000000 LCDCON2 0X4D000004 LCDCON3 0X4D000008 LCDCON4 ...

Page 59

... PRODUCT OVERVIEW Table 1-4. S3C2440A Special Registers (Sheet 5 of 14) (Continued) Register Address Name (B. Endian) NAND Flash NFCONF 0x4E000000 NFCONT 0x4E000004 NFCMD 0x4E000008 NFADDR 0x4E00000C NFDATA 0x4E000010 NFMECC0 0x4E000014 NFMECC1 0x4E000018 NFSECC 0x4E00001C NFSTAT 0x4E000020 NFESTAT0 0x4E000024 NFESTAT1 0x4E000028 NFMECC0 0x4E00002C NFMECC1 0x4E000030 ...

Page 60

... S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 6 of 14) (Continued) Register Address Name (B. Endian) Camera Interface CISRCFMT 0x4F000000 CIWDOFST 0x4F000004 CIGCTRL 0x4F000008 CICOYSA1 0x4F000018 CICOYSA2 0x4F00001C CICOYSA3 0x4F000020 CICOYSA4 0x4F000024 CICOCBSA1 0x4F000028 CICOCBSA2 0x4F00002C CICOCBSA3 0x4F000030 CICOCBSA4 0x4F000034 CICOCRSA1 0x4F000038 CICOCRSA2 ...

Page 61

... PRODUCT OVERVIEW Table 1-4. S3C2440A Special Registers (Sheet 7 of 14) (Continued) Register Address Name (B. Endian) UART ULCON0 0x50000000 UCON0 0x50000004 UFCON0 0x50000008 UMCON0 0x5000000C UTRSTAT0 0x50000010 UERSTAT0 0x50000014 UFSTAT0 0x50000018 UMSTAT0 0x5000001C UTXH0 0x50000023 URXH0 0x50000027 UBRDIV0 0x50000028 ULCON1 0x50004000 UCON1 0x50004004 UFCON1 ...

Page 62

... S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 8 of 14) (Continued) Register Name Address (B. Endian) PWM Timer TCFG0 0x51000000 TCFG1 0x51000004 TCON 0x51000008 TCNTB0 0x5100000C TCMPB0 0x51000010 TCNTO0 0x51000014 TCNTB1 0x51000018 TCMPB1 0x5100001C TCNTO1 0x51000020 TCNTB2 0x51000024 TCMPB2 0x51000028 TCNTO2 0x5100002C TCNTB3 ...

Page 63

... PRODUCT OVERVIEW Table 1-4. S3C2440A Special Registers (Sheet 9 of 14) (Continued) Register Name Address (B. Endian) USB Device FUNC_ADDR_REG 0x52000143 PWR_REG 0x52000147 EP_INT_REG 0x5200014B USB_INT_REG 0x5200015B EP_INT_EN_REG 0x5200015F USB_INT_EN_REG 0x5200016F FRAME_NUM1_REG 0x52000173 FRAME_NUM2_REG 0x52000177 INDEX_REG 0x5200017B EP0_CSR 0x52000187 IN_CSR1_REG 0x52000187 IN_CSR2_REG 0x5200018B MAXP_REG 0x52000183 ...

Page 64

... S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 10 of 14) (Continued) Register Name Address (B. Endian) USB Device (Continued) EP2_DMA_TTC_H 0x5200022F EP3_DMA_CON 0x52000243 EP3_DMA_UNIT 0x52000247 EP3_DMA_FIFO 0x5200024B EP3_DMA_TTC_L 0x5200024F EP3_DMA_TTC_M 0x52000253 EP3_DMA_TTC_H 0x52000257 EP4_DMA_CON 0x5200025B EP4_DMA_UNIT 0x5200025F EP4_DMA_FIFO 0x52000263 EP4_DMA_TTC_L 0x52000267 EP4_DMA_TTC_M 0x5200026B ...

Page 65

... PRODUCT OVERVIEW Table 1-4. S3C2440A Special Registers (Sheet 11 of 14) (Continued) Register Address Name (B. Endian) I/O port GPACON 0x56000000 GPADAT 0x56000004 GPBCON 0x56000010 GPBDAT 0x56000014 GPBUP 0x56000018 GPCCON 0x56000020 GPCDAT 0x56000024 GPCUP 0x56000028 GPDCON 0x56000030 GPDDA1T 0x56000034 GPDUP 0x56000038 GPECON 0x56000040 GPEDAT 0x56000044 GPEUP ...

Page 66

... S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 12 of 14) (Continued) Register Address Name (B. Endian) i/o port (continued) EINTFLT0 0x56000094 EINTFLT1 0x56000098 EINTFLT2 0x5600009C EINTFLT3 0x560000A0 EINTMASK 0x560000A4 EINTPEND 0x560000A8 GSTATUS0 0x560000AC GSTATUS1 0x560000B0 GSTATUS2 0x560000B4 GSTATUS3 0x560000B8 GSTATUS4 0x560000BC MSLCON 0x560000CC RTC ...

Page 67

... PRODUCT OVERVIEW Table 1-4. S3C2440A Special Registers (Sheet 13 of 14) (Continued) Register Address Name (B. Endian) A/D Converter ADCCON 0x58000000 ADCTSC 0x58000004 ADCDLY 0x58000008 ADCDAT0 0x5800000C ADCDAT1 0x58000010 ADCUPDN 0x58000014 SPI SPCON0,1 0x59000000,20 SPSTA0,1 0x59000004,24 SPPIN0,1 0x59000008,28 SPPRE0,1 0x5900000C,2C SPTDAT0,1 0x59000010,30 SPRDAT0,1 0x59000014,34 SD Interface SDICON ...

Page 68

... S3C2440A RISC MICROPROCESSOR Table 1-4. S3C2440A Special Registers (Sheet 14 of 14) (Continued) Register Address Name (B. Endian) AC97 Audio-CODEC Interface AC_GLBCTRL 0x5B000000 AC_GLBSTAT 0x5B000004 AC_CODEC_CMD 0x5B000008 AC_CODEC_STAT 0x5B00000C AC_PCMADDR 0x5B000010 AC_MICADDR 0x5B000014 AC_PCMDATA 0x5B000018 AC_MICDATA 0x5B00001C Cautions on S3C2440A Special Registers 1. In the little endian mode ‘L’, endian address must be used. In the big endian mode ‘B’ endian address must be used ...

Page 69

... S3C2440A RISC MICROPROCESSOR 2 PROGRAMMER'S MODEL OVERVIEW S3C2440A is developed using the advanced ARM920T core, which has been designed by Advanced RISC Machines, Ltd. PROCESSOR OPERATING STATES From the programmer's point of view, the ARM920T can be in one of the two states: ARM state which executes 32-bit, word-aligned ARM instructions THUMB state is a state which can execute 16-bit, halfword-aligned THUMB instructions ...

Page 70

... Word is addressed by byte address of most significant byte Least significant byte is at lowest address Word is addressed by byte address of least significant byte S3C2440A RISC MICROPROCESSOR Word Address Word Address ...

Page 71

... S3C2440A RISC MICROPROCESSOR OPERATING MODES ARM920T supports seven modes of operation: User (usr): The normal ARM program execution state FIQ (fiq): Designed to support a data transfer or channel process IRQ (irq): Used for general-purpose interrupt handling Supervisor (svc): Protected mode for the operating system ...

Page 72

... ARM State Program Status Registers CPSR CPSR SPSR_ SPSR_ fiq svc S3C2440A RISC MICROPROCESSOR IRQ Undefined ...

Page 73

... S3C2440A RISC MICROPROCESSOR The THUMB State Register Set The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each privileged mode ...

Page 74

... THUMB State Stack Pointer (SP) Link Register (LR) Program Counter (PC) (CPSR) (SPSR) Figure 2-5. Mapping of THUMB State Registers onto ARM State Registers 2-6 S3C2440A RISC MICROPROCESSOR ARM State r10 r11 r12 Stack Pointer (r13) Link Register (r14) ...

Page 75

... S3C2440A RISC MICROPROCESSOR Accessing Hi-Registers in THUMB State In THUMB state, registers R8-R15 ("Hi registers") are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage. A value may be transferred from a register in the range R0- register register and from a Hi register register, using special variants of the MOV instruction ...

Page 76

... The remaining bits in the PSRs are reserved. When changing a PSR's flag or control bits, you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero. 2-8 S3C2440A RISC MICROPROCESSOR ...

Page 77

... S3C2440A RISC MICROPROCESSOR M[4:0] Mode 10000 User 10001 FIQ 10010 IRQ 10011 Supervisor 10111 Abort 11011 Undefined 11111 System Reserved bits The remaining bits in the PSR's are reserved. While changing a PSR's flag or control bits, you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero ...

Page 78

... Copies the SPSR back to the CPSR 3. Clears the interrupt disable flags, if they were set on entry An explicit switch back to THUMB state is never needed, since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception. 2-10 S3C2440A RISC MICROPROCESSOR NOTE ...

Page 79

... S3C2440A RISC MICROPROCESSOR Exception Entry/Exit Summary Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler. Return Instruction BL MOV PC, R14 SWI MOVS PC, R14_svc UDEF MOVS PC, R14_und FIQ SUBS PC, R14_fiq, #4 IRQ SUBS PC, R14_irq, #4 ...

Page 80

... After fixing the reason for the abort, the handler should execute the following irrespective of the state (ARM or Thumb): SUBS PC,R14_abt,#4 SUBS PC,R14_abt,#8 This restores both the PC and the CPSR, and retries the aborted instruction. 2-12 S3C2440A RISC MICROPROCESSOR ; for a prefetch abort for a data abort ...

Page 81

... S3C2440A RISC MICROPROCESSOR Software Interrupt The Software Interrupt Instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb): MOV PC,R14_svc This restores the PC and CPSR, and returns to the instruction following the SWI. ...

Page 82

... FIQ vector. A normal return from FIQ will cause the data abort handler to resume execution. Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection. The time for this exception entry should be added to worst-case FIQ latency calculations. 2-14 S3C2440A RISC MICROPROCESSOR ...

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... S3C2440A RISC MICROPROCESSOR INTERRUPT LATENCIES The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchronizer (Tsyncmax if asynchronous), plus the time for the longest instruction to complete (Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data abort entry (Texc), plus the time for FIQ entry (Tfiq) ...

Page 84

... PROGRAMMER'S MODEL 2-16 S3C2440A RISC MICROPROCESSOR NOTES ...

Page 85

... S3C2440A RISC MICROPROCESSOR 3 ARM INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set in the ARM920T core. FORMAT SUMMARY The following figure shows the ARM instruction set Cond Opcode Cond ...

Page 86

... MLA Multiply accumulate MOV Move register or constant 3-2 NOTES Table 3-1. The ARM Instruction Set Instruction S3C2440A RISC MICROPROCESSOR Action Rd Op2 + Carry Rd Op2 Rd AND Op2 R15: = address Rd AND NOT Op2 R14: = R15, R15: = address R15: = Rn, T bit: = Rn[0] (Coprocessor-specific) ...

Page 87

... S3C2440A RISC MICROPROCESSOR Table 3-1. The ARM Instruction Set (Continued) Mnemonic MRC Move from coprocessor register to CPU register MRS Move PSR status/flags to register MSR Move register to PSR status/flags MUL Multiply MVN Move negative register ORR OR RSB Reverse subtract RSC Reverse subtract with Carry ...

Page 88

... N clear V set V clear C set and Z clear C clear or Z set N equals V N not equal clear AND (N equals V) Z set OR (N not equal to V) (ignored) S3C2440A RISC MICROPROCESSOR Meaning equal not equal unsigned higher or same unsigned lower negative positive or zero overflow no overflow ...

Page 89

... S3C2440A RISC MICROPROCESSOR BRANCH AND EXCHANGE (BX) This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. This instruction performs a branch by copying the contents of a general register, Rn, into the Program Counter, PC. The branch causes a pipeline flush and refill from the address specified by Rn. This instruction also permits the instruction set to be exchanged ...

Page 90

... Branch and change to THUMB state. Assemble subsequent code as THUMB instructions Generate branch target to word aligned address hence bit 0 is low and so change back to ARM state. Branch and change back to ARM state. Word alignment Assemble subsequent code as ARM instructions S3C2440A RISC MICROPROCESSOR – ...

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... S3C2440A RISC MICROPROCESSOR BRANCH AND BRANCH WITH LINK (B, BL) The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction encoding is shown in Figure 3-3, below Cond 101 L Branch instruction contains a signed 2's complement 24 bit offset. This is shifted left two bits, sign extended to 32 bits, and added to the PC ...

Page 92

... BL sub+ROM ADDS R1,#1 BLCC sub 3-8 S3C2440A RISC MICROPROCESSOR ; Assembles to 0xEAFFFFFE (note effect of PC offset). ; Always condition used as default. ; Compare R1 with zero and branch to fred if R1 was zero, otherwise continue. ; Continue to next instruction. ; Call subroutine at computed address. ; Add 1 to register 1, setting CPSR flags on the result then call subroutine if ...

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... S3C2440A RISC MICROPROCESSOR DATA PROCESSING The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3- Cond 00 L OpCode [15:12] Destination register 0 = Branch [19:16] 1st operand register 0 = Branch [20] Set condition codes not after condition codes ...

Page 94

... Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are used only to perform tests and to set the condition codes on the result and always have the S bit set. The instructions and their effects are listed in Table 3-3. 3-10 S3C2440A RISC MICROPROCESSOR ...

Page 95

... S3C2440A RISC MICROPROCESSOR CPSR FLAGS The data processing operations can be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result. If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be unaffected. The C flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is LSL #0), the Z flag will be set if and only if the result is all zeros, and the N flag will be set to the logical value of bit 31 of the result ...

Page 96

... Shift type 01 = logical right 00 = logical left 11 = rotate right 10 = arithmetic right [11:8] Shift register Shift amount specified in bottom-byte of Rs Figure 3-5. ARM Shift Operations Contents of Rm Value of Operand 2 Figure 3-6. Logical Shift Left NOTE S3C2440A RISC MICROPROCESSOR logical right 11 = rotate right 0 0 ...

Page 97

... S3C2440A RISC MICROPROCESSOR The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit the carry output. Logical shift right zero is redundant the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR # specified ...

Page 98

... This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents shown in Figure 3-10 3-14 Contents of Rm Value of Operand 2 Figure 3-9. Rotate Right Contents of Rm Value of Operand 2 Figure 3-10. Rotate Right Extended S3C2440A RISC MICROPROCESSOR carry out 1 0 carry out ...

Page 99

... S3C2440A RISC MICROPROCESSOR Register Specified Shift Amount Only the least significant byte of the contents used to determine the shift amount. Rs can be any general register other than R15. If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the CPSR C flag will be passed on as the shifter carry output ...

Page 100

... Data processing with register specified shift Data processing with PC written Data processing with register specified shift and PC written NOTE and I are as defined sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle) respectively. 3-16 NOTE Table 3-4. Incremental Cycle Times S3C2440A RISC MICROPROCESSOR Cycles +1I ...

Page 101

... S3C2440A RISC MICROPROCESSOR ASSEMBLER SYNTAX MOV,MVN (single operand instructions). <opcode>{cond}{S} Rd,<Op2> CMP,CMN,TEQ,TST (instructions which do not produce a result). <opcode>{cond} Rn,<Op2> AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC <opcode>{cond}{S} Rd,Rn,<Op2> where: <Op2> Rm{,<shift>} or,<#expression> {cond} A two-character condition mnemonic. See Table 3-2. {S} Set condition codes if S present (implied for CMP, CMN, TEQ, TST). ...

Page 102

... The SPSR register which is accessed depends on the mode at the time of execution. For example, only SPSR_fiq is accessible when the processor is in FIQ mode. You must not specify R15 as the source or destination register. Also, do not attempt to access an SPSR in User mode, since no such register exists. 3-18 S3C2440A RISC MICROPROCESSOR ...

Page 103

... S3C2440A RISC MICROPROCESSOR MRS (transfer PSR contents to a register Cond 00010 MSR (transfer register contents to PSR Cond 00010 MSR (transfer register contents or immediate value to PSR flag bits only Cond 001111 Rd [15:12] Destination Register ...

Page 104

... No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits. INSTRUCTION CYCLE TIMES PSR transfers take 1S incremental cycles, where S is defined as Sequential (S-cycle). 3-20 S3C2440A RISC MICROPROCESSOR ; Take a copy of the CPSR. ; Clear the mode bits. ; Select new mode ; Write back the modified CPSR. ...

Page 105

... S3C2440A RISC MICROPROCESSOR ASSEMBLY SYNTAX MRS - transfer PSR contents to a register MRS{cond} Rd,<psr> MSR - transfer register contents to PSR MSR{cond} <psr>,Rm MSR - transfer register contents to PSR flag bits only MSR{cond} <psrf>,Rm The most significant four bits of the register contents are written to the N,Z,C & V flags respectively. ...

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... [15:12][11:8][3:0] Operand Registers [19:16] Destination Register [20] Set Condition Code not after condition codes 1 = Set condition codes [21] Accumulate 0 = Multiply only 1 = Multiply and accumulate [31:28] Condition Field Figure 3-12. Multiply Instructions Result 0xFFFFFF38 S3C2440A RISC MICROPROCESSOR ...

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... S3C2440A RISC MICROPROCESSOR If the Operands Are Interpreted as Signed Operand A has the value -10, operand B has the value 20, and the result is -200 which is correctly represented as 0xFFFFFF38. If the Operands Are Interpreted as Unsigned Operand A has the value 4294967286, operand B has the value 20 and the result is 85899345720, which is represented as 0x13FFFFFF38, so the least significant 32 bits are 0xFFFFFF38 ...

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... If bits [32:24] of the multiplier operand are all zero or all one all other cases. ASSEMBLER SYNTAX MUL{cond}{S} Rd,Rm,Rs MLA{cond}{S} Rd,Rm,Rs,Rn {cond} Two-character condition mnemonic. See Table 3-2.. {S} Set condition codes if S present Rd, Rm, Rs and Rn Expressions evaluating to a register number other than R15. EXAMPLES MUL R1,R2,R3 MLAEQS R1,R2,R3,R4 3-24 S3C2440A RISC MICROPROCESSOR ; R1:=R2*R3 ; Conditionally R1:=R2*R3+R4, Setting condition codes. ...

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... S3C2440A RISC MICROPROCESSOR MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL, MLAL) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-13. The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results. ...

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... For Unsigned Instructions UMULL, UMLAL: If bits [31:8] of the multiplier operand are all zero. If bits [31:16] of the multiplier operand are all zero. If bits [31:24] of the multiplier operand are all zero. In all other cases. S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively. 3-26 S3C2440A RISC MICROPROCESSOR ...

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... S3C2440A RISC MICROPROCESSOR ASSEMBLER SYNTAX Mnemonic UMULL{cond}{S} RdLo,RdHi,Rm,Rs UMLAL{cond}{S} RdLo,RdHi,Rm,Rs SMULL{cond}{S} RdLo,RdHi,Rm,Rs SMLAL{cond}{S} RdLo,RdHi,Rm,Rs where: {cond} Two-character condition mnemonic. See Table 3-2. {S} Set condition codes if S present RdLo, RdHi, Rm, Rs Expressions evaluating to a register number other than R15. EXAMPLES UMULL R1,R4,R2,R3 UMLALS R1,R5,R2,R3 Table 3-5. Assembler Syntax Descriptions ...

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... Post: add offset after transfer 1 = Pre: add offset before transfer [25] Immediate Offset 0 = Offset is an immediate value [11:0] Offset 11 Immediate [11:0] Unsigned 12-bit immediate offset Shift [3:0] Offset register [11:4] Shift applied to Rm [31:28] Condition Field Figure 3-14. Single Data Transfer Instructions S3C2440A RISC MICROPROCESSOR 12 11 Offset ...

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... S3C2440A RISC MICROPROCESSOR OFFSETS AND AUTO-INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction second register (possibly shifted in some way). The offset may be added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification may be performed either before (pre-indexed, P=1) or after (post-indexed, P=0) the base is used as the transfer address ...

Page 114

... That is, bit 31 of the register being stored always appears on data bus output 31. 3-30 memory LDR from word aligned address memory LDR from address offset by 2 Figure 3-15. Little-Endian Offset Addressing S3C2440A RISC MICROPROCESSOR register register ...

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... S3C2440A RISC MICROPROCESSOR USE OF R15 Write-back must not be specified if R15 is specified as the base register (Rn). While using R15 as the base register, you must remember it contains an address of 8 bytes on from the address of the current instruction. R15 must not be specified as the register offset (Rm). ...

Page 116

... General shift operation (see data processing instructions) but you cannot specify the shift amount by a register. {!} Writes back the base register (set the W bit) if! is present. 3-32 S3C2440A RISC MICROPROCESSOR offset of zero offset of <expression> bytes offset of +/- contents of index register, shifted by <shift> offset of <expression> bytes offset of +/- contents of index register, shifted as by < ...

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... S3C2440A RISC MICROPROCESSOR EXAMPLES STR R1,[R2,R4]! STR R1,[R2],R4 LDR R1,[R2,#16] LDR R1,[R2,R3,LSL#2] LDREQB R1,[R6,#5] STR R1,PLACE PLACE ; Store R1 at R2+R4 (both of which are registers) ; and write back address to R2. ; Store and write back R2+R4 to R2. ; Load R1 from contents of R2+16, but don't write back. ; Load R1 from contents of R2+R3*4. ; Conditionally load byte at R6+5 into ...

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... Write-back write-back 1 = Write address into base [23] Up/Down 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing 0 = Post: add/subtract offset after transfer 1 = Pre: add/subtract offset bofore transfer [31:28] Condition Field S3C2440A RISC MICROPROCESSOR 0000 ...

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... S3C2440A RISC MICROPROCESSOR Cond 000 P U Figure 3-17. Halfword and Signed Data Transfer with Immediate Offset and Auto-Indexing OFFSETS AND AUTO-INDEXING The offset from the base may be either a 8-bit unsigned binary immediate value in the instruction second register. The 8-bit offset is formed by concatenating bits and bits the instruction word, such that bit 11 becomes the MSB and bit 0 becomes the LSB ...

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... A halfword store (STRH) repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0. The external memory system should activate the appropriate halfword subsystem to store the data. Note that the address must be halfword aligned, if bit 0 of the address is HIGH this will cause unpredictable behaviour. 3-36 S3C2440A RISC MICROPROCESSOR ...

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... S3C2440A RISC MICROPROCESSOR Big-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 31 through the supplied address word boundary, on data bus inputs 23 through word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte ...

Page 122

... ARM920T pipelining. In this case base write-back should not be specified. {!} Writes back the base register (set the W bit present. 3-38 S3C2440A RISC MICROPROCESSOR offset of zero offset of <expression> bytes offset of +/- contents of index register offset of <expression> bytes ...

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... S3C2440A RISC MICROPROCESSOR EXAMPLES LDRH R1,[R2,-R3]! STRH R3,[R4,#14] LDRSB R8,[R2],#-223 LDRNESH R11,[R0] HERE STRH R5, [PC,#(FRED-HERE-8)]; FRED ; Load R1 from the contents of the halfword address ; contained in R2-R3 (both of which are registers) ; and write back address Store the halfword R14+14 but don't write back. ...

Page 124

... Load PSR or force user mode [23] Up/Down Bit 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing Bit 0 = Post: add offset after transfer 1 = Pre: add offset bofore transfer [31:28] Condition Field Figure 3-18. Block Data Transfer Instructions S3C2440A RISC MICROPROCESSOR 0 Register list ...

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... S3C2440A RISC MICROPROCESSOR ADDRESSING MODES The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the up/ down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last. The lowest register also gets transferred to/from the lowest memory address. By way of illustration, consider the transfer of R1, R5 and R7 in the case where Rn=0x1000 and write back of the modified base is required (W=1) ...

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... ARM INSTRUCTION SET Rn Rn 3-42 0x100C 0x1000 0x0FF4 1 0x100C 0x1000 0x0FF4 3 Figure 3-20. Pre-Increment Addressing 0x100C 0x1000 0x0FF4 1 0x100C 0x1000 R5 R1 0x0FF4 Rn 3 Figure 3-21. Post-Decrement Addressing S3C2440A RISC MICROPROCESSOR 0x100C R1 0x1000 0x0FF4 2 R7 0x100C R5 R1 0x1000 0x0FF4 4 0x100C 0x1000 R1 0x0FF4 2 0x100C R7 0x1000 R5 R1 0x0FF4 4 ...

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... S3C2440A RISC MICROPROCESSOR Rn USE OF THE S BIT When the S bit is set in a LDM/STM instruction it depends on R15 is available in the transfer list and on the type of instruction. The S bit should only be set if the instruction is to execute in a privileged mode. LDM with R15 in Transfer List and S Bit Set (Mode Changes) If the instruction is a LDM then SPSR_< ...

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... INSTRUCTION CYCLE TIMES Normal LDM instructions take and LDM PC takes (n+1 incremental cycles, where S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STM instructions take (n-1 incremental cycles to execute, where n is the number of words transferred. 3-44 S3C2440A RISC MICROPROCESSOR ...

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... S3C2440A RISC MICROPROCESSOR ASSEMBLER SYNTAX <LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^} where: {cond} Two character condition mnemonic. See Table 3- expression evaluating to a valid register number <Rlist> A list of registers and register ranges enclosed in {} (e.g. {R0,R2-R7,R10}). {!} If present requests write-back (W=1), otherwise W=0. {^} If present set S bit to load the CPSR along with the PC, or force transfer of user bank when in privileged mode ...

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... These instructions may be used to save state on subroutine entry, and restore it efficiently on return to the calling routine: STMED SP!,{R0-R3,R14} BL somewhere LDMED SP!,{R0-R3,R15} 3-46 S3C2440A RISC MICROPROCESSOR ; Unstack 3 registers. ; Save all registers. ; R15 (SP), CPSR unchanged. ; R15 (SP), CPSR <- SPSR_mode ; (allowed only in privileged modes). ; Save user mode regs on stack ...

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... S3C2440A RISC MICROPROCESSOR SINGLE DATA SWAP (SWP Cond 00010 The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-23. The data swap instruction is used to swap a byte or word quantity between a register and external memory. This instruction is implemented as a memory read followed by a memory write which are “ ...

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... Expressions evaluating to valid register numbers Examples SWP R0,R1,[R2] SWPB R2,R3,[R4] SWPEQ R0,R0,[R1] 3-48 S3C2440A RISC MICROPROCESSOR ; Load R0 with the word addressed by R2, and ; store R1 at R2. ; Load R2 with the byte addressed by R4, and ; store bits R4. ; Conditionally swap the contents of the ; word addressed by R1 with R0. ...

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... S3C2440A RISC MICROPROCESSOR SOFTWARE INTERRUPT (SWI) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-24, below Cond 1111 The software interrupt instruction is used to enter Supervisor mode in a controlled manner. The instruction causes the software interrupt trap to be taken, which effects the mode change ...

Page 134

... LDR R15,[R2,R1,LSL#2] WriteIRtn LDMFD R13,{R0-R2,R15}^ 3-50 S3C2440A RISC MICROPROCESSOR ; Get next character from read stream. ; Output a "k" to the write stream. ; Conditionally call supervisor with 0 in comment field. ; SWI entry point ; Addresses of supervisor routines ; SWI has routine required in bits 8-23 and data (if any) in ...

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... The S3C2440A, unlike some other ARM-based processors, does not have an external coprocessor interface. It does not have a on-chip coprocessor also. So then all coprocessor instructions will cause the undefined instruction trap to be taken on the S3C2440A. These coprocessor instructions can be emulated by the undefined trap handler. Even though external coprocessor can not be connected to the S3C2440A, the coprocessor instructions are still described here in full for completeness ...

Page 136

... Where present is evaluated to a constant and placed in the CP field EXAMPLES CDP p1,10,c1,c2,c3 CDPEQ p2,5,c1,c2,c3,2 3-52 S3C2440A RISC MICROPROCESSOR ; Request coproc operation CR2 and CR3, and put the result in CR1 flag is set request coproc operation 5 (type CR2 and CR3, and put the result in CR1. ...

Page 137

... S3C2440A RISC MICROPROCESSOR COPROCESSOR DATA TRANSFERS (LDC, STC) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-26. This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessors's registers directly to memory. ARM920T is responsible for supplying the memory address and the coprocessor supplies or accepts the data and controls the number of words transferred ...

Page 138

... Instruction cycle times Coprocessor data transfer instructions take (n-1 incremental cycles to execute, where: n The number of words transferred. b The number of cycles spent in the coprocessor busy-wait loop and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. 3-54 S3C2440A RISC MICROPROCESSOR ...

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... S3C2440A RISC MICROPROCESSOR ASSEMBLER SYNTAX <LDC|STC>{cond}{L} p#,cd,<Address> LDC Load from memory to coprocessor STC Store from coprocessor to memory {L} When present perform long transfer (N=1), otherwise perform short transfer (N=0) {cond} Two character condition mnemonic. See Table 3-2.. p# The unique number of the required coprocessor cd An expression evaluating to a valid coprocessor register number that is placed in the CRd field < ...

Page 140

... CP Opc L CRn Rd [3:0] Coprocessor Operand Register [7:5] Coprocessor Information [11:8] Coprocessor Number [15:12] ARM Source/Destination Register [19:16] Coprocessor Source/Destination Register [20] Load/Store Bit 0 = Store to coprocessor 1 = Load from coprocessor [21] Coprocessor Operation Mode [31:28] Condition Field S3C2440A RISC MICROPROCESSOR CP CRm 0 ...

Page 141

... S3C2440A RISC MICROPROCESSOR TRANSFERS TO R15 When a coprocessor register transfer to ARM920T has R15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the and V flags respectively. The other bits of the transferred word are ignored, and the PC and other CPSR bits are unaffected by the transfer. ...

Page 142

... ASSEMBLER SYNTAX The assembler has no mnemonics for generating this instruction adopted in the future for some specified use, suitable mnemonics will be added to the assembler. Until such time, this instruction must not be used. 3-58 xxxxxxxxxxxxxxxxxxxx Figure 3-28. Undefined Instruction S3C2440A RISC MICROPROCESSOR xxxx 1 ...

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... S3C2440A RISC MICROPROCESSOR INSTRUCTION SET EXAMPLES The following examples show ways in which the basic ARM920T instructions can combine to give efficient code. None of these methods saves a great deal of execution time (although they may save some), mostly they just save code. USING THE CONDITIONAL INSTRUCTIONS ...

Page 144

... Overflow in signed multiply accumulate with a 32 bit result SMLAL Rd,Rt,Rm,Rn TEQ Rt,Rd, ASR#31 BNE overflow 3-60 S3C2440A RISC MICROPROCESSOR ; Enter with numbers in Ra and Rb. ; Bit to control the division. ; Move Rb until greater than Ra. ; Test for possible subtraction. ; Subtract if ok, ; Put relevant bit into result ; Shift control bit ...

Page 145

... S3C2440A RISC MICROPROCESSOR 5. Overflow in unsigned multiply accumulate with a 64 bit result UMULL Rl,Rh,Rm,Rn ADDS Rl,Rl,Ra1 ADC Rh,Rh,Ra2 BCS overflow 6. Overflow in signed multiply accumulate with a 64 bit result SMULL Rl,Rh,Rm,Rn ADDS Rl,Rl,Ra1 ADC Rh,Rh,Ra2 BVS overflow Overflow checking is not applicable to unsigned and signed multiplies with a 64-bit result, since overflow does not occur in such calculations ...

Page 146

... This is not quite optimal, but close. An example of its non-optimality is multiply by 45 which is done by: RSB Rb,Ra,Ra,LSL#2 RSB Rb,Ra,Rb,LSL#2 ADD Rb,Ra,Rb,LSL# 2 rather than by: ADD Rb,Ra,Ra,LSL#3 ADD Rb,Rb,Rb,LSL#2 3-62 S3C2440A RISC MICROPROCESSOR ; Multiply and then Multiply Multiply by 2 and add in next digit ; Multiply Multiply by 4*3 Multiply by 4*11 Multiply Multiply by 5 ...

Page 147

... S3C2440A RISC MICROPROCESSOR LOADING A WORD FROM AN UNKNOWN ALIGNMENT BIC Rb,Ra,#3 LDMIA Rb,{Rd,Rc} AND Rb,Ra,#3 MOVS Rb,Rb,LSL#3 MOVNE Rd,Rd,LSR Rb RSBNE Rb,Rb,#32 ORRNE Rd,Rd,Rc,LSL Rb ; Enter with address in Ra (32 bits) uses ; Rb, Rc result in Rd. Note d must be less than c e.g. 0,1 ; Get word aligned address ; Get 64 bits containing answer ; Correction factor in bytes ...

Page 148

... ARM INSTRUCTION SET 3-64 S3C2440A RISC MICROPROCESSOR NOTES ...

Page 149

... S3C2440A RISC MICROPROCESSOR 4 THUMB INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16-bit versions of ARM instruction sets (32-bit format). The ARM instructions are reduced to 16-bit versions.Thumb instructions, at the cost of versatile functions of the ARM instruction sets. The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM920T core ...

Page 150

... R Rlist Rb Rlist Cond Softset8 Value8 Offset11 Offset Figure 4-1. THUMB Instruction Set Formats S3C2440A RISC MICROPROCESSOR Move Shifted register Rd Add/subtract Move/compare/add/ subtract immediate Rd ALU operations Rd/Hd Hi register operations /branch exchange PC-relative load Rd Load/store with register offset Rd Load/store sign-extended ...

Page 151

... S3C2440A RISC MICROPROCESSOR OPCODE SUMMARY The following table summarizes the THUMB instruction set. For further information about a particular instruction please refer to the sections listed in the right-most column. Mnemonic ADC Add with Carry ADD Add AND AND ASR Arithmetic Shift Right B Unconditional branch ...

Page 152

... Subtract TST Test bits NOTES: 1. The condition codes are unaffected by the format 5, 12 and 13 versions of this instruction. 2. The condition codes are unaffected by the format 5 version of this instruction. 4-4 Instruction Lo-Register Operand S3C2440A RISC MICROPROCESSOR Hi-Register Condition Operand Codes Set Y – Y – Y – Y – ...

Page 153

... S3C2440A RISC MICROPROCESSOR FORMAT 1: MOVE SHIFTED REGISTER OPERATION These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown in Table 4-2. All instructions in this group set the CPSR condition codes. OP THUMB Assembler 00 LSL Rd, Rs, #Offset5 01 LSR Rd, Rs, #Offset5 ...

Page 154

... All instructions in this format have an equivalent ARM instruction as shown in Table 4-2. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LSR R2, R5, #27 4-6 S3C2440A RISC MICROPROCESSOR ; Logical shift right the contents and store the result in R2.Set condition codes on the result. ...

Page 155

... S3C2440A RISC MICROPROCESSOR FORMAT 2: ADD/SUBTRACT OPERATION These instructions allow the contents register or a 3-bit immediate value to be added to or subtracted from a Lo register. The THUMB assembler syntax is shown in Table 4-3. All instructions in this group set the CPSR condition codes. ...

Page 156

... All instructions in this format have an equivalent ARM instruction as shown in Table 4-3. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD R0, R3, R4 SUB R6, R2, #6 4-8 S3C2440A RISC MICROPROCESSOR ; and set condition codes on the result and set condition codes. ...

Page 157

... S3C2440A RISC MICROPROCESSOR FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE OPERATIONS The instructions in this group perform operations between a Lo register and an 8-bit immediate value. The THUMB assembler syntax is shown in Table 4-4. All instructions in this group set the CPSR condition codes. OP THUMB Assembler ...

Page 158

... THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES MOV R0, #128 CMP R2, #62 ADD R1, #255 SUB R6, #145 4-10 S3C2440A RISC MICROPROCESSOR ; R0 := 128 and set condition codes ; Set condition codes 255 and set condition codes ; 145 and set condition codes ...

Page 159

... S3C2440A RISC MICROPROCESSOR FORMAT 4: ALU OPERATIONS OPERATION The following instructions perform ALU operations register pair. All instructions in this group set the CPSR condition codes. OP THUMB Assembler 0000 AND Rd, Rs 0001 EOR Rd, Rs 0010 LSL Rd, Rs 0011 ...

Page 160

... CMP R2, R6 MUL R0, R7 4-12 S3C2440A RISC MICROPROCESSOR ; EOR R4 and set condition codes ; Rotate Right R1 by the value in R0, store ; the result in R1 and set condition codes ; Subtract the contents of R3 from zero, ; Store the result in R5. Set condition codes – R3 ...

Page 161

... S3C2440A RISC MICROPROCESSOR FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE OPERATION There are four sets of instructions in this group. The first three allow ADD, CMP and MOV operations to be performed between Lo and Hi registers pair of Hi registers. The fourth, BX, allows a Branch to be performed which may also be used to switch processor state ...

Page 162

... Causes the processor to enter ARM state. Bit Causes the processor to enter THUMB state. The action for this instruction is undefined, and should not be used. 4-14 S3C2440A RISC MICROPROCESSOR ARM equivalent CMP Hd, Hs Compare two registers in the range 8-15. Set the condition code flags on the result ...

Page 163

... S3C2440A RISC MICROPROCESSOR EXAMPLES Hi-Register Operations ADD PC, R5 CMP R4, R12 MOV R15, R14 Branch and Exchange ADR R1,outofTHUMB MOV R11,R1 BX R11 ALIGN CODE32 outofTHUMB USING R15 AS AN OPERAND If R15 is used as an operand, the value will be the address of the instruction + 4 with bit 0 cleared. Executing THUMB state from a non-word aligned address will result in unpredictable execution. ...

Page 164

... PC is forced ensure it is word aligned. 4- [7:0] Immediate Value [10:8] Destination Register Figure 4-7. Format 6 ARM equivalent LDR Rd, [R15, #Imm] S3C2440A RISC MICROPROCESSOR Word 8 Description Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the PC. Load the word from the resulting address into Rd. 0 ...

Page 165

... S3C2440A RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LDR R3,[PC,#844] ; Load into R3 the word found at the address formed by adding 844 to PC.bit[ forced to zero. ...

Page 166

... FORMAT 7: LOAD/STORE WITH REGISTER OFFSET 4- [2:0] Source/Destination Register [5:3] Base Register [8:6] Offset Register [10] Byte/Word Flag 0 = Transfer word quantity 1 = Transfer byte quantity [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 4-8. Format 7 S3C2440A RISC MICROPROCESSOR ...

Page 167

... S3C2440A RISC MICROPROCESSOR OPERATION These instructions transfer byte or word values between registers and memory. Memory addresses are pre-indexed using an offset register in the range 0-7. The THUMB assembler syntax is shown in Table 4- THUMB assembler 0 0 STR Rd, [Rb, Ro STRB Rd, [Rb, Ro LDR Rd, [Rb, Ro] ...

Page 168

... Operand not sing-extended 1 = Operand sing-extended [11] H Flag Figure 4-9. Format 8 Table 4-9. Summary of Format 8 Instructions ARM equivalent STRH Rd, [Rb, Ro] LDRH Rd, [Rb, Ro] LDRSB Rd, [Rb, Ro] LDRSH Rd, [Rb, Ro] S3C2440A RISC MICROPROCESSOR Description Store halfword: Add Ro to base address in Rb. Store bits 0- the resulting address. ...

Page 169

... S3C2440A RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-9. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH R4, [R3, R0] LDSB R2, [R7, R1] LDSH R3, [R4, R2] ; Store the lower 16 bits the address formed by adding R0 to R3. ...

Page 170

... FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET 4- Offset5 [2:0] Source/Destination Register [5:3] Base Register [10:6] Offset Register [11] Load/Store Flag 0 = Store to memory 1 = Load from memory [12] Byte/Word Flad 0 = Transfer word quantity 1 = Transfer byte quantity Figure 4-10. Format 9 S3C2440A RISC MICROPROCESSOR ...

Page 171

... S3C2440A RISC MICROPROCESSOR OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7-bit offset. The THUMB assembler syntax is shown in Table 4-10 THUMB assembler 0 0 STR Rd, [Rb, #Imm LDR Rd, [Rb, #Imm STRB Rd, [Rb, #Imm LDRB Rd, [Rb, #Imm] ...

Page 172

... Base Register [10:6] Immediate Value [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 4-11. Format 10 ARM equivalent STRH Rd, [Rb, #Imm] LDRH Rd, [Rb, #Imm] S3C2440A RISC MICROPROCESSOR Description Add #Imm to base address in Rb and store bits the resulting address. ...

Page 173

... S3C2440A RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-11. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH R6, [R1, #56] LDRH R4, [R7, #4] ; Store the lower 16 bits the address formed by adding 56 R1 ...

Page 174

... Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 4-12. Format 11 ARM equivalent STR Rd, [R13 #Imm] LDR Rd, [R13 #Imm] S3C2440A RISC MICROPROCESSOR Word 8 Description Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the SP (R7). Store the contents the resulting address. ...

Page 175

... S3C2440A RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-12. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STR R4, [SP,#492] ; Store the contents the address formed by adding 492 to SP (R13) ...

Page 176

... SP Figure 4-13. Format 12 Table 4-13. Load Address ARM equivalent ADD Rd, R15, #Imm ADD Rd, R13, #Imm S3C2440A RISC MICROPROCESSOR Word 8 Description Add #Imm to the current value of the program counter (PC) and load the result into Rd. Add #Imm to the current value of the stack pointer (SP) and load the result into Rd. ...

Page 177

... S3C2440A RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-13. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD R2, PC, #572 ADD R6, SP, #212 ; 572, but don't set thecondition codes. ...

Page 178

... Note that the THUMB opcode will contain 67 as the Word7 value and S= (R13 104, but don't set the condition codes. ; Note that the THUMB opcode will contain 26 as the Word7 value and S=1. S3C2440A RISC MICROPROCESSOR SWord 7 Description Add #Imm to the stack pointer (SP). Add #-Imm to the stack pointer (SP). ...

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... S3C2440A RISC MICROPROCESSOR FORMAT 14: PUSH/POP REGISTERS OPERATION The instructions in this group allow registers 0-7 and optionally pushed onto the stack, and registers 0-7 and optionally popped off the stack. The THUMB assembler syntax is shown in Table 4-15. The stack is always assumed to be Full Descending. ...

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... EXAMPLES PUSH {R0-R4,LR} POP {R2,R6,PC} 4-32 S3C2440A RISC MICROPROCESSOR ; Store R0,R1,R2,R3,R4 and R14 (LR) at the stack pointed to by R13 (SP) and update R13. Useful at start of a sub-routine to save workspace and return address. ; Load R2,R6 and R15 (PC) from the stack pointed to by R13 (SP) and update R13.Useful to restore workspace ...

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... S3C2440A RISC MICROPROCESSOR FORMAT 15: MULTIPLE LOAD/STORE OPERATION These instructions allow multiple loading and storing of Lo registers. The THUMB assembler syntax is shown in the following table. Table 4-16. The Multiple Load/Store Instructions L THUMB assembler 0 STMIA Rb!, { Rlist } 1 LDMIA Rb!, { Rlist } INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-16 ...

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... BCS label BCC label BMI label BPL label BVS label BVC label BHI label S3C2440A RISC MICROPROCESSOR SOffset 8 Description Branch if Z set (equal) Branch if Z clear (not equal) Branch if C set (unsigned higher or same) Branch if C clear (unsigned lower) Branch if N set (negative) ...

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... S3C2440A RISC MICROPROCESSOR Table 4-17. The Conditional Branch Instructions (Continued) L THUMB assembler 1001 BLS label 1010 BGE label 1011 BLT label 1100 BGT label 1101 BLE label NOTES: 1. While label specifies a full 9-bit two's complement address, this must always be halfword-aligned (ie with bit 0 set to 0) since the assembler actually places label > ...

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... Move the address of the next instruction into LR, move CPSR to SPSR, load the SWI vector address (0x8) into the PC. Switch to ARM state and enter SVC mode. ; Take the software interrupt exception. Enter Supervisor mode with 18 as the requested SWI number. S3C2440A RISC MICROPROCESSOR 0 Value 8 Description ...

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... S3C2440A RISC MICROPROCESSOR FORMAT 18: UNCONDITIONAL BRANCH OPERATION This instruction performs a PC-relative Branch. The THUMB assembler syntax is shown below. The branch offset must take account of the prefetch operation, which causes the word (4 bytes) ahead of the current instruction ...

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... BL is placed in LR and bit set. The branch offset must take account of the prefetch operation, which causes the word (4 bytes) ahead of the current instruction 4- [10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit 0 = Offset high 1 = Offset low Figure 4-20. Format 19 S3C2440A RISC MICROPROCESSOR Offset 0 ...

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... S3C2440A RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction. L THUMB assembler 0 BL label 1 EXAMPLES BL faraway next faraway Table 4-20. The BL Instruction ARM equivalent none OffsetHigh << 12 temp := next instruction address OffsetLow << temp | 1 ; Unconditionally Branch to 'faraway' and place following instruction address, ie " ...

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... Effectively this is any of the multiplications followed by a final shift. This allows the following additional constants to be multiplied. 6, 10, 12, 14, 18, 20, 24, 28, 30, 34, 36, 40, 48, 56, 60, 62 ..... (2..5) LSL Ra, Ra, #n 4-40 S3C2440A RISC MICROPROCESSOR ; MOV Ra, Rb, LSL #n ; ADD Ra, Rb, Rb, LSL #n ; RSB Ra, Rb, Rb, LSL #n ; MOV Ra, Rb, LSL #n ; RSB Ra, Ra, #0 ...

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... S3C2440A RISC MICROPROCESSOR GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code. Thumb code ;signed_divide ;Get abs value of R0 into R3 ASR R2, R0, #31 EOR R0, R2 SUB R3, R0, R2 ;SUB always sets flag so go & report division necessary ...

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... RSBMI a2, a2 MOV pc, lr 4-42 S3C2440A RISC MICROPROCESSOR ; Get dividend/divisor signs back ; Result sign ; Negate if result sign = - 1 ; Negate remainder if dividend sign = - 1 Effectively zero a4 as top bit will be shifted out later ; Justification stage shifts 1 bit at a time ; NB: LSL #1 is always succeeds ...

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... S3C2440A RISC MICROPROCESSOR DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code. Thumb Code udiv10 ...

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... THUMB INSTRUCTION SET 4-44 S3C2440A RISC MICROPROCESSOR NOTES ...

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... S3C2440A RISC MICROPROCESSOR 5 MEMORY CONTROLLER OVERVIEW The S3C2440A memory controller provides memory control signals that are required for external memory access. The S3C2440A has the following features: — Little/Big endian (selectable by a software) — Address space: 128Mbytes per bank (total 1GB/8 banks) — ...

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... SROM (nGCS2) 0x1000_0000 SROM (nGCS1) 0x0800_0000 SROM (nGCS0) 0x0000_0000 [ Not using NAND flash for boot ROM ] Figure 5-1. S3C2440A Memory Map after Reset 5-2 [ Using NAND flash for boot ROM ] NOTE SROM means ROM or SRAM type memory S3C2440A RISC MICROPROCESSOR OM[1: SROM/SDRAM 2MB/4MB/8MB/16MB (nGCS7) ...

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... S3C2440A RISC MICROPROCESSOR Address 2MB Start address 0x3000_0000 0x3000_0000 End address 0x301F_FFFF 0X303F_FFFF Start address 0x3020_0000 0x3040_0000 End address 0X303F_FFFF 0X307F_FFFF NOTE: Bank 6 and 7 must have the same memory size. Table 5-1. Bank 6/7 Addresses 4MB 8MB 16MB Bank 6 0x3000_0000 0x3000_0000 0X307F_FFFF 0X30FF_FFFF ...

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... MEMORY ADDR. PIN 5-4 OM0 (Operating Mode S3C2440A ADDR. S3C2440A ADDR. @ 8-bit DATA BUS @ 16-bit DATA BUS S3C2440A RISC MICROPROCESSOR Booting ROM Data width Nand Flash Mode 16-bit 32-bit Test Mode S3C2440A ADDR. @ 32-bit DATA BUS ...

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... S3C2440A RISC MICROPROCESSOR SDRAM BANK ADDRESS PIN CONNECTION EXAMPLE Table 5-2. SDRAM Bank Address Configuration Example Bank Size Bus Width 2MByte x8 x16 4MB x16 x16 8MB x16 x32 x8 x8 x16 x16 x32 16MB x32 x8 x8 x16 x16 x32 x32 x8 x16 32MB x16 ...

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... The nWE signal have the same relation with nOE. HCLK ADDR nGCS Tacs nOE nWAIT DATA(R) Figure 5-2. S3C2440A External nWAIT Timing Diagram (Tacc=4) 5-6 Tacc=4 Tcos S3C2440A RISC MICROPROCESSOR Delayed Sampling nWAIT ...

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... S3C2440A RISC MICROPROCESSOR nXBREQ/nXBACK Pin Operation If nXBREQ is asserted, the S3C2440A will respond by lowering nXBACK. If nXBACK=L, the address/data bus and memory control signals are in Hi-Z state as shown in Table 1-1. After nXBREQ is de-asserted, the nXBACK will also be de-asserted. HCLK SCLK SCKE, A[24:0] D[31:0], nGCS nOE,nWE nWBE nXBREQ nXBACK Figure 5-3 ...

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... nWE nWBE0 A10 A9 nOE nOE A11 A10 nCE nGCSn A12 A11 A13 A12 A14 A13 A15 A14 A16 A15 S3C2440A RISC MICROPROCESSOR nWE nOE nGCSn DQ0 D8 DQ1 D9 DQ2 D10 DQ3 D11 DQ4 D12 DQ5 D13 ...

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