21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

CaseQFP  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Page 41
42
Page 42
43
Page 43
44
Page 44
45
Page 45
46
Page 46
47
Page 47
48
Page 48
49
Page 49
50
Page 50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
Page 45/164:

Prefetchable Read Transactions

Download datasheet (812Kb)Embed
PrevNext
Table 18. Read Transaction Prefetching (Sheet 2 of 2)
Memory read
Memory read line
Memory read multiple
See
Section 5.3
for detailed information about prefetchable and nonprefetchable address spaces.
4.6.1

Prefetchable Read Transactions

A prefetchable read transaction is a read transaction where the 21150 performs speculative Dword
reads, transferring data from the target before it is requested from the initiator. This behavior allows
a prefetchable read transaction to consist of multiple data transfers. However, byte enable bits
cannot be forwarded for all data phases as is done for the single data phase of the nonprefetchable
read transaction. For prefetchable read transactions, the 21150 forces all byte enable bits to be
turned on for all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions, as well
as for memory read transactions that fall into prefetchable memory space.
The amount of data that is prefetched depends on the type of transaction. The amount of
prefetching may also be affected by the amount of free buffer space available in the 21150, and by
any read address boundaries encountered.
Prefetching should not be used for those read transactions that have side effects in the target device,
that is, control and status registers, FIFOs, and so on. The target device’s base address register or
registers indicate if a memory address region is prefetchable.
4.6.2
Nonprefetchable Read Transactions
A nonprefetchable read transaction is a read transaction where the 21150 requests 1–and only
1–Dword from the target and disconnects the initiator after delivery of the first Dword of read data.
Unlike prefetchable read transactions, the 21150 forwards the read byte enable information for the
data phase.
Nonprefetchable behavior is used for I/O and configuration read transactions, as well as for
memory read transactions that fall into nonprefetchable memory space.
If extra read transactions could have side effects, for example, when accessing a FIFO, use
nonprefetchable read transactions to those locations. Accordingly, if it is important to retain the
value of the byte enable bits during the data phase, use nonprefetchable read transactions. If these
locations are mapped in memory space, use the memory read command and map the target into
nonprefetchable (memory-mapped I/O) memory space to utilize nonprefetching behavior.
Preliminary
Datasheet
Type of Transaction
Read Behavior
Downstream: Prefetching used if
address in prefetchable Upstream:
Prefetching used if prefetch
disable is off (default)
Prefetching always used
Prefetching always used
21150
37