21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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Page 78/164:

Data Parity Errors

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21150
The 21150 asserts p_serr_l and sets the signaled system error bit in the status register, if both
of the following conditions are met:
— The SERR# enable bit is set in the command register.
— The parity error response bit is set in the bridge control register.
7.2

Data Parity Errors

When forwarding transactions, the 21150 attempts to pass the data parity condition from one
interface to the other unchanged, whenever possible, to allow the master and target devices to
handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that occurs
when a parity error is detected and the way in which the parity condition is forwarded across the
21150.
7.2.1
Configuration Write Transactions to 21150 Configuration Space
When the 21150 detects a data parity error during a Type 0 configuration write transaction to 21150
configuration space, the following events occur:
If the parity error response bit is set in the command register, the 21150 asserts p_trdy_l and
writes the data to the configuration register. The 21150 also asserts p_perr_l.
If the parity error response bit is not set, the 21150 does not assert p_perr_l.
The 21150 sets the detected parity error bit in the status register, regardless of the state of the
parity error response bit.
7.2.2
Read Transactions
When the 21150 detects a parity error during a read transaction, the target drives data and data
parity, and the initiator checks parity and conditionally asserts PERR#.
For downstream transactions, when the 21150 detects a read data parity error on the secondary bus,
the following events occur:
The 21150 asserts s_perr_l two cycles following the data transfer, if the secondary interface
parity error response bit is set in the bridge control register.
The 21150 sets the detected parity error bit in the secondary status register.
The 21150 sets the data parity detected bit in the secondary status register, if the secondary
interface parity error response bit is set in the bridge control register.
The 21150 forwards the bad parity with the data back to the initiator on the primary bus.
If the data with the bad parity is prefetched and is not read by the initiator on the primary bus,
the data is discarded and the data with bad parity is not returned to the initiator.
The 21150 completes the transaction normally.
For upstream transactions, when the 21150 detects a read data parity error on the primary bus, the
following events occur:
70
Preliminary
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