21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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The first 8 bits contain the PRSNT#<1:0> signal values for four slots, and these bits control the
s_clk_o<3:0> outputs. If one or both of the PRSNT#<1:0> signals are 0, that indicates that a card is
present in the slot and therefore the secondary clock for that slot is not masked. If these clocks are
connected to devices and not to slots, one or both of the bits should be tied low to enable the clock.
The next 5 bits are the clock mask for devices; each bit enables or disables the clock for one device.
These bits control the s_clk_o<8:4> outputs: 0 enables the clock, and 1 disables the clock.
Bit 13 is the clock enable bit for s_clk_o<9>, which is connected to the 21150’s s_clk input.
If desired, the assignment of s_clk_o clock outputs to slots, devices, and the 21150’s s_clk input
can be rearranged from the assignment shown here. However, it is important that the serial data
stream format match the assignment of s_clk_o outputs.
The gpio pin serial protocol is designed to work with two 74F166 8-bit shift registers.
Figure 19
shows how the serial mask circuitry may be implemented for a motherboard with four
slots.
Figure 19. Example of gpio Clock Mask Implementation on the System Board
Preliminary
Datasheet
msk_in
21150
CE#
gpio<0>
CP
MR#
gpio<2>
PE
CE#
CP
MR#
PE
vss
vcc
21150
vss
vcc
Q7
74F166
7
6
5
4
3
2
1
0
D
s
Q7
74F166
prsnt0#<0>
7
prsnt0#<1>
6
prsnt1#<0>
5
prsnt1#<1>
4
prsnt2#<0>
3
prsnt2#<1>
2
prsnt3#<0>
1
prsnt3#<1>
0
LJ-04644.AI5
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