73M2910L-IG TDK Corporation, 73M2910L-IG Datasheet
73M2910L-IG
Related parts for 73M2910L-IG
73M2910L-IG Summary of contents
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... DESCRIPTION The 73M2910L high performance micro-controller is based on the industry standard implemented in an advanced submicron CMOS process. The processor has the attributes of the 8032, including instruction cycle time, UART, timers, interrupts, 256 bytes of programmable I/O. The architecture has been optimized for low power portable modem or communication applications by integrating unique features with the core CPU ...
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... Signum Systems, 11992 Challenger Court, Moorpark, CA 93021 (805) 523-9774. 8032 REFERENCE This Document will describe the features unique to the 73M2910L. Please refer to a 8032 Programmer’s Guide, Description for details on the instruction set, timers, UART, interrupt control, and memory structure. peripherals ...
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... The core chip provides 8 sources of interrupt; 3 external interrupts, 3 timer interrupts, a serial port interrupt, and an HDLC interrupt. An external interrupt and an HDLC interrupt are unique to the 73M2910L. They do not exist in a normal 8032 product. Previously unused bits in the IE and IP registers are now serving functions for these additional interrupt sources ...
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... BIT 7 Bit activity bit cleared by a read of this register. If the activity bit is set it will prevent the 73M2910L from entering sleep mode. BIT 6 When bit CLK1OUT will be OSC/1.5 if bit and bit ...
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... If PCON.1 is set, the 73M2910L goes into its lowest power mode where the oscillator is halted. The total current consumption in this state should be less than 10 µa. The 73M2910L will start its oscillator and begin to return to normal operation when either a reset occurs, when a falling (rising if corresponding direction bit is set) edge of an unmasked external interrupt from pins INT(2:0) is detected, or when the USR5 (1:0) pins change to a state according to the USR5 port register ...
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Microcontroller REGISTER DESCRIPTION USR PROGRAMMABLE I/O Port Control USR1, USR2, USR3, USR4, USR5 The core chip provides 32 user I/O pins. Each pin is programmed separately as either an input output by a bit in a direction ...
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After a reset, the USR1 pins will present a high impedance output state and the input values will not be driven from the pin, but will be driven internally. The pins will assume normal I/O operation once ...
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Microcontroller USR3 PORT (continued) USR3 I/O Port Direction (DIR3) External Address 0001h Byte Addressable Reset State FFh BIT 7 BIT 6 DIR3.7 DIR3.6 This register is used to designate the USR3 pins as either inputs or outputs. If the register ...
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BSEN BS1 Don’t care BANK 3 BANK 2 BANK 1 BANK 0 BS0 A15’ ...
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Microcontroller USR PROGRAMMABLE I/O (continued) USR4 PORT USR4 Port Data External Address 0003h Byte Addressable Reset State 00h BIT 7 BIT 6 USR4.7 USR4.6 Bits in this register will be asserted on the USR4(7:0) pins if the corresponding direction register ...
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... CS4 (USR4.4) CS5 (USR4.5) CS6 (USR4.6) CS7 (USR4.7) NOTE: External addresses 0000H-00FFH may not be read. These are reserved for 73M2910L internally defined registers USR5 PORT USR5 Port Register External Address 0006h Byte Addressable Reset State 60h BIT 7 BIT 6 USR5EN USR5.0 USR5 ...
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Microcontroller USR5 PORT (continued) BIT 4 USR5.0 Polarity Bit 4 determines which edge or level is used in the wakeup detection circuit. A low level selects a rising transition and the true pin value of USR5.0 to the wakeup detection ...
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... This register controls the basic set-up of the DTE and modem pins RXD, TXD, PRXD, and PTXD. BIT 7 WRXD Bit 7 allows the processor to write directly to the 73M2910L RXD output pin. The value of bit 7 will appear at the RXD pin only if bit and bit ...
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... BITS 1,0 PTXD Control Bit 1 and bit 0 control the source of the 73M2910L PTXD output pin. This output goes to the modem’s TX data input. The source of this signal can be the core’s HDLC TX output, the DTE’s TXD output (clear channel), or the value written into bit 6 of this register. ...
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BIT 5 CRC Preset Value Bit 5 selects the reset value for the CRC generator and receiver. If this bit is set the CRC generator and receiver are initialized to ones and if this bit is reset ...
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Microcontroller HDLC CONTROL REGISTERS HDLC TX CONTROL REGISTER (HTXC) SFR ADDRESS 0C2h Byte Addressable Reset State 00h BIT 7 BIT This register is used to control the source of data that appears on the PTXD pin. Bits ...
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BIT 0 Send Flag When bit 0 is set, a pattern of 7E will be transmitted to the PTXD output as soon as either the next data byte or CRC has completed transmission will be inserted during the ...
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Microcontroller HDLC STATUS REGISTER (HSTAT) SFR ADDRESS 0C3h BIT 4 RX Overrun When bit 4 is set, a receive overrun condition has been detected. This is a condition where the HDLC has received a new byte, but the last received ...
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BIT 7 Transmitter Ready Interrupt Enable When bit 7 is set, an HDLC interrupt will be generated if bit 0 (TX RDY) of the HDLC Interrupt Register is also set. If bit 7 is reset HDLC ...
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Microcontroller HDLC INTERRUPT ENABLE REGISTER (HIE) SFR ADDRESS 0C4h BIT 0 Flag Detect Interrupt Enable When bit 0 is set, a HDLC interrupt will be generated if bit 0 (FLAG DETECT) of the HDLC Status (HSTAT) Register is also set. ...
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RX DATA REGISTER (RXD) SFR ADDRESS 0C6h Byte Addressable Read Only Register Reset State XXh BIT 7 BIT 6 BIT DAT7 DAT6 DAT5 BITS 7-0 Received Data Byte Bit 7 through bit 0 is the received data ...
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Microcontroller REGISTER DESCRIPTION CRC GENERATION SET COMPUTE AND2 DATA C 16 CCITT 16 Bit CRC CCITT Type The CRC check field is generated by the transmitter. The computation starts with the first transmitted bit after the opening ...
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RESET (option to set) COMPUTE AND2 DATA CRC CRC 16 The CRC check field is generated by the transmitter. The computation starts with the first transmitted ...
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Microcontroller CRC GENERATION (continued) SET COMPUTE AND2 DATA CRC Polynomial CRC 32 The CRC check field is generated by the transmitter. The computation starts with the first ...
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... CLKOUT2 O Clock output 1.8432 MHz clock for an external UART given an oscillator frequency of 11.0592 MHz, 22.1184 MHz, 18.432 MHz, or 13.824 MHz. TXD I Serial input port to 73M2910L from DTE same as RXD UART input. RXD O Serial output port of 73M2910L UART to DTE. PTXCLK I Input clock used to transmit data PTXD. ...
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Microcontroller MEMORY MAPS BANK 3 BANK 2 ADDRESS 32K - 64K FIGURE 7: 128K of Bank-Selected Program Memory FFFFh External RAM (MOVX data, addr) 0100h On chip externally FFh addressed memory mapped register (MOVX data, addr) Internal RAM Indirect addressing ...
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... CLK CTRL RCAP2L RCAP2H TL2 TH2 *TXC *HSTAT *HIE *HINT *IDIR TL0 TL1 TH0 TH1 DPL DPH *Unique to the 73M2910L. There may not be an equivalent function on an 8032. FIGURE 9: 73M2910L SFR Map 27 Microcontroller CSEN USR5 *HRXD *HTXD C7 BF ...
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Microcontroller ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Recommended conditions apply unless otherwise specified. PARAMETER Supply Voltage Pin Input Voltage Storage Temperature RECOMMENDED OPERATING CONDITIONS Supply Voltage Oscillator Frequency Operating Temperature DC CHARACTERISTICS PARAMETER Input Low Voltage V (Except PTXCLK, PRXCK, OSCIN, ...
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... CIO AC TIMING The 73M2910L timing is very similar to the 8032 except in AD(7:0), the multiplexed address data port known as port 0 in the 8032. Its timing has been altered somewhat to allow more address setup time for peripheral program ROM and memory mapped peripherals. This is important for operation above 22 MHz. The 8032 has a “ ...
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Microcontroller TOSC OSCIN ALE AD(7:0) A(15:0) FIGURE 10: External Program Memory Read Cycle TLHLL TLLPL TPLAZ TPLIV TLLAX A0-A7 TAVIV TAVLL 30 TPLPH High Z TPXIZ INSTR IN TPXIX ...
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AC TIMING (continued) EXTERNAL DATA READ AND WRITE TIMING PARAMETER RD Pulse Width TRLRH WR Pulse Width TWLWH RD Low to Valid Data In TRLDV Data Hold After RD TRHDX Data Float After RD TRHDZ ALE Low to Valid Data ...
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Microcontroller ELECTRICAL SPECIFICATIONS TOSC OSCIN ALE AD (7:0) A (15:0) TOSC OSCIN ALE AD (7:0) A (15:0) (continued) TLLWL A0-A7 INSTR IN A0-A7 FIGURE 11: External Data Memory Write Cycle TLLWL TRLAZ A0-A7 INSTR IN A0-A7 TLLDV FIGURE 12: External ...
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... USER INTERFACE Note: The 73D2248A Device Set is comprised of the 73M2910L and 73K224L. 73D2248A DEVICE SET TXA RXA AG1 AG0 FIGURE 13: Modem Block Diagram 33 Microcontroller TELEPHONE INTERFACE TXA RXA ...
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Microcontroller ELECTRICAL SPECIFICATIONS VCC R32 TR 2.4K D6 R33 MR 2.4K D7 R39 TD 2.4K D8 R34 RD 2.4K D9 R35 CD 2.4K D10 R36 AA 2.4K D11 R37 OH 2.4K D12 R38 HS 2. EXCLK ...
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FIGURE 15: Telephone Interface 35 Microcontroller ...
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Microcontroller ELECTRICAL SPECIFICATIONS 20k 20k 20k DUMB 2 7 V.25 V.25 V.25-2 SW DIP-4 GND DCD CTS RXD EXCLK DTR RTS TXD DSR ...
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CLKOUT2 RST WR RD ALE AD0 - AD7 USR 4.7 USR 4.0 RXCLK TXCLK MTXD MRXD EXCLK A0 - A15 ALE ...
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Microcontroller ELECTRICAL SPECIFICATIONS 100-Pin PGA (For development purposes only; not a production package.) PIN # ...
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PGA (continued) (For development purposes only; not a production package.) PIN # SIGNAL NAME M6 GND N6 RD B13 OSCIN C12 NO CONNECT A13 NO CONNECT B12 NO CONNECT A12 CLK2OUT B11 VPD A11 CLK1OUT B10 TXD A10 RXD ...
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Microcontroller MECHANICAL SPECIFICATIONS 100-Lead QFP PIN No. 1 Indicator + 0.30 (0.012) 0.40 (0.016) 0.65 (0.026) Typ. 19.62 (0.772) 20.12 (0.792) 23.77 (0.936) 24.03 (0.946) 13.62 (0.536) 14.12 (0.556) 2.6 (0.102) 2.8 (0.110) 0.15 (0.006) 0.50 (0.020) 17.77 (0.700) 18.03 ...
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... CAUTION: Use handling procedures necessary for a static sensitive component USR5 USR5.1 76 USR3.1 75 USR3.0 74 USR4.0 73 USR4.1 72 USR4.2 71 USR4.3 70 USR4.4 69 USR4.5 68 USR4.6 67 USR4.7 66 VND 65 VPD 64 USR2.0 63 USR2.1 62 USR2.2 61 USR2.3 60 USR2.4 59 USR25 58 USR2.6 57 USR2 PACKAGE MARK 73M2910L-IG 04/24/00 - rev. G ...