RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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Page 16/74:

Electrical Specifications

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®
®
LV Intel
Pentium
III Processor 512K
3.0

Electrical Specifications

3.1
Processor System Bus Signal Groups
To simplify the following discussion, the processor system bus signals have been combined into
groups by buffer type. All P6 family processor system bus outputs are open drain and require
termination resistors. However, the LV Intel Pentium
termination for AGTL signals. This makes it unnecessary to place termination resistors on the
platform, except in the case of the RESET# signal, which still requires external termination.
AGTL input signals have differential input buffers that use V
output signals require termination to 1.25 V. In this document, the term “AGTL Input” refers to the
AGTL input group and to the AGTL I/O group when this group is receiving signals. Similarly,
“AGTL Output” refers to the AGTL output group and to the AGTL I/O group when this group is
driving signals.
The PWRGOOD signal input is a 1.8 V signal level and must be pulled up to V
VTT_PWRGD is not 1.8 V tolerant and must be connected to V
(A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI#, SLP#, and STPCLK#) are
only 1.5 V tolerant and must be pulled up to V
open drain and must be pulled to the appropriate level to meet the input specifications of the
interfacing device.
The groups and the signals contained within each group are shown in
Interface” on page 59
Table 3.
System Bus Signal Groups (Sheet 1 of 2)
Group Name
AGTL Input
AGTL Output
AGTL I/O
1.5 V CMOS Input
1.8 V CMOS Input
1.5 V Open Drain Output
3.3 V Open Drain Output
1.25 V input
Clock
2.5 V Clock Input
NOTES:
1. V
is the power supply for the core logic.
CCCORE
2. PLL1 and PLL2 are power/ground for the PLL analog section. See
details.
3. V
is the power supply for the system bus buffers.
TT
4. V
is the voltage reference for the AGTL input buffers.
REF
5. V
is system ground.
SS
16
processor 512K includes on-die
III
. The CMOS, APIC, and TAP outputs are
CC CMOS1.5
for a description of these signals.
Signals
BPRI#, DEFER#, RESET#, RSP#, BR1#
PRDY#
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#,
BPM[1:0]#, BR0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#,
LOCK#, REQ[4:0]#, RP#, RS[2:0]#, TRDY#
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#,
SMI#, STPCLK#
PWRGOOD
FERR#, IERR#, THERMTRIP#
BSEL[1:0], VID[3:0, 25mV]
VTT_PWRGD
BCLK, BCLK# (Differential Mode)
BCLK (Single Ended Mode)
as a reference signal. AGTL
REF
. The
CC CMOS1.8
1.25 V). Other CMOS inputs
(
TT
Table
3. Refer to
“Processor
“Voltage Planes” on page 21
for
Datasheet