III Processor 512K
System Bus, Clock, APIC, TAP, CMOS, and Open-Drain AC
The processor system bus timings specified in this section are defined at the processor core (pads).
All system bus AC specifications for the AGTL signal group are relative to the crossing point of the
rising edge of the BCLK input and falling edge of the BCLK# input. All AGTL timings are
referenced to V
CMOS, and open-drain signals except PWRGOOD are referenced to 1.0 V. All minimum and
maximum specifications are at points within the power supply ranges shown in
junction temperatures (Tj) in the range 0 C to 100 C. Tj must be less than or equal to 100 C for
all functional processor states.
Table 12. System Bus Clock AC Specifications (Differential)
System Bus Frequency
BCLK Period - average
BCLK Period – Instantaneous minimum
BCLK Cycle to Cycle Jitter
BCLK Rise Time
BCLK Fall Time
Vcross for 1 V swing
Rise/Fall Time Matching
BCLK Duty Cycle
1. All AC timings for AGTL and CMOS signals are referenced to the BCLK and BCLK# crossing point.
2. Measured on differential waveform: defined as (BCLK - BCLK#).
3. Not 100% tested. Specified by design/characterization.
4. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that the clock driver be
designed to meet a period stability specification into a test load of 10 to 20 pF. This should be measured on the
rising edge of adjacent BCLKs at the BCLK and BCLK# crossing point. The jitter present must be accounted for
as a component of BCLK skew between devices. Period difference is measured around 0 V crossing points.
5. Measurement taken from common mode waveform. Measure rise/fall time from 0.41 to 0.86 V. Rise/fall time
matching is defined as “the instantaneous difference between maximum BCLK rise (fall) and minimum BCLK#
fall (rise) time, or minimum BCLK rise (fall) and maximum BCLK# fall (rise) time”. This parameter is designed to
guard waveform symmetry.
6. Rise time is measured from -0.35 V to 0.35 V and fall time is measured from 0.35 V to -0.35 V.
7. Measured on common mode waveform - includes every rise/fall crossing.
for both “0” and “1” logic levels unless otherwise specified. All APIC, TAP,