RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
22
Page 22
23
Page 23
24
Page 24
25
Page 25
26
Page 26
27
Page 27
28
Page 28
29
Page 29
30
Page 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Page 30/74:

AC Specifications

Download datasheet (664Kb)Embed
PrevNext
®
®
LV Intel
Pentium
III Processor 512K
3.11

AC Specifications

3.11.1
System Bus, Clock, APIC, TAP, CMOS, and Open-Drain AC
Specifications
The processor system bus timings specified in this section are defined at the processor core (pads).
All system bus AC specifications for the AGTL signal group are relative to the crossing point of the
rising edge of the BCLK input and falling edge of the BCLK# input. All AGTL timings are
referenced to V
REF
CMOS, and open-drain signals except PWRGOOD are referenced to 1.0 V. All minimum and
maximum specifications are at points within the power supply ranges shown in
junction temperatures (Tj) in the range 0 C to 100 C. Tj must be less than or equal to 100 C for
all functional processor states.
Table 12. System Bus Clock AC Specifications (Differential)
Symbol
System Bus Frequency
T1
BCLK Period - average
T1abs
BCLK Period – Instantaneous minimum
T2
BCLK Cycle to Cycle Jitter
T5
BCLK Rise Time
T6
BCLK Fall Time
Vcross for 1 V swing
Rise/Fall Time Matching
BCLK Duty Cycle
NOTES:
1. All AC timings for AGTL and CMOS signals are referenced to the BCLK and BCLK# crossing point.
2. Measured on differential waveform: defined as (BCLK - BCLK#).
3. Not 100% tested. Specified by design/characterization.
4. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that the clock driver be
designed to meet a period stability specification into a test load of 10 to 20 pF. This should be measured on the
rising edge of adjacent BCLKs at the BCLK and BCLK# crossing point. The jitter present must be accounted for
as a component of BCLK skew between devices. Period difference is measured around 0 V crossing points.
5. Measurement taken from common mode waveform. Measure rise/fall time from 0.41 to 0.86 V. Rise/fall time
matching is defined as “the instantaneous difference between maximum BCLK rise (fall) and minimum BCLK#
fall (rise) time, or minimum BCLK rise (fall) and maximum BCLK# fall (rise) time”. This parameter is designed to
guard waveform symmetry.
6. Rise time is measured from -0.35 V to 0.35 V and fall time is measured from 0.35 V to -0.35 V.
7. Measured on common mode waveform - includes every rise/fall crossing.
30
for both “0” and “1” logic levels unless otherwise specified. All APIC, TAP,
Parameter
Min
7.5
7.3
175
175
0.51
45%
Table 6
and
Typ
Max
Unit
Figure
Notes
133
MHz
7.7
ns
12
ns
200
ps
2, 3,
467
ps
12
467
ps
12
0.76
V
11
325
ps
55%
Datasheet
1
2
2
4
2,
6
2,
6
7
5
2