III Processor 512K
Table 14. Valid LV Intel Pentium
NOTE: While other combinations of bus and core frequencies are defined, operation at frequencies other
than those listed above will not be validated by Intel and are not guaranteed. The frequency multiplier
is programmed into the processor when it is manufactured and it cannot be changed.
Table 15. AGTL Signal Groups AC Specifications
internally terminated to V
AGTL Output Valid Delay
AGTL Input Setup Time
AGTL Input Hold Time
RESET# Pulse Width
1. All AC timings for AGTL signals are referenced to the crossing point of the BCLK rising edge and the
BCLK# falling edge for differential clocking and to the BCLK rising edge at 1.25 V for single-ended
clocking. All AGTL signals are referenced at V REF .
2. RESET# can be asserted (active) asynchronously, but must be de-asserted synchronously.
3. This specification is for a minimum 0.40 V swing from V
4. This specification is for a maximum 0.80 V swing from V
5. Valid after V
Table 16. CMOS and Open-Drain Signal Groups AC Specifications
1.5 V Input Pulse Width, except PWRGOOD
LINT[1:0] Input Pulse Width
PWRGOOD Inactive Pulse Width
1. All AC timings for CMOS and open-drain signals are referenced to the crossing point of the BCLK rising
edge and BCLK# falling edge for Differential Clocking and to the rising edge of BCLK at 1.25 V for single-
ended clocking. All CMOS and open-drain signals are referenced at 1.0 V.
2. Minimum output pulse width on CMOS outputs is two BCLKs.
3. This specification only applies when the APIC is enabled and the LINT1 or LINT0 signal is configured as an
edge triggered interrupt with fixed delivery, otherwise specification T14 applies.
4. When driven inactive, or after V
until all the voltage planes meet the voltage tolerance specifications in
BCLK# have met the BCLK, BCLK# AC specifications in
PWRGOOD must rise error-free and monotonically to 1.8 V.
5. For active and inactive states
Processor 512K Frequencies
; load = 50
– 200 mV to V
– 0.8 V to V
, and BCLK, BCLK# become stable and PWRGOOD is asserted.
and BCLK, BCLK# become stable. PWRGOOD must remain
for at least 2 µs.