RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Page 32/74:

Processor Frequencies

Download datasheet (664Kb)Embed
PrevNext
®
®
LV Intel
Pentium
III Processor 512K
Table 14. Valid LV Intel Pentium
BCLK Frequency
(MHz)
133
133
133
NOTE: While other combinations of bus and core frequencies are defined, operation at frequencies other
than those listed above will not be validated by Intel and are not guaranteed. The frequency multiplier
is programmed into the processor when it is manufactured and it cannot be changed.
Table 15. AGTL Signal Groups AC Specifications
R
internally terminated to V
TT
Symbol
T7
AGTL Output Valid Delay
T8
AGTL Input Setup Time
T9
AGTL Input Hold Time
T10
RESET# Pulse Width
NOTES:
1. All AC timings for AGTL signals are referenced to the crossing point of the BCLK rising edge and the
BCLK# falling edge for differential clocking and to the BCLK rising edge at 1.25 V for single-ended
clocking. All AGTL signals are referenced at V REF .
2. RESET# can be asserted (active) asynchronously, but must be de-asserted synchronously.
3. This specification is for a minimum 0.40 V swing from V
4. This specification is for a maximum 0.80 V swing from V
5. Valid after V
CC CORE
Table 16. CMOS and Open-Drain Signal Groups AC Specifications
Symbol
1.5 V Input Pulse Width, except PWRGOOD
T14
and LINT[1:0]
T14B
LINT[1:0] Input Pulse Width
T15
PWRGOOD Inactive Pulse Width
NOTES:
1. All AC timings for CMOS and open-drain signals are referenced to the crossing point of the BCLK rising
edge and BCLK# falling edge for Differential Clocking and to the rising edge of BCLK at 1.25 V for single-
ended clocking. All CMOS and open-drain signals are referenced at 1.0 V.
2. Minimum output pulse width on CMOS outputs is two BCLKs.
3. This specification only applies when the APIC is enabled and the LINT1 or LINT0 signal is configured as an
edge triggered interrupt with fixed delivery, otherwise specification T14 applies.
4. When driven inactive, or after V
below V
until all the voltage planes meet the voltage tolerance specifications in
IL18,MAX
BCLK# have met the BCLK, BCLK# AC specifications in
PWRGOOD must rise error-free and monotonically to 1.8 V.
5. For active and inactive states
32
Processor 512K Frequencies
III
Core Frequency
Frequency Multiplier
(MHz)
6
800
7
933
8
1000
2
; V
=
/
V
; load = 50
TT
REF
3
TT
Parameter
Min
0.40
0.95
1
1
– 200 mV to V
REF
– 0.8 V to V
TT
, V
, and BCLK, BCLK# become stable and PWRGOOD is asserted.
TT
Parameter
Min
2
6
2
, V
and BCLK, BCLK# become stable. PWRGOOD must remain
CC CORE
TT
Table 20
Power-on Configuration
bits [27,25:22]
0, 1011
0, 1100
0, 1101
1
Max
Unit
Figure
Notes
3.25
ns
13
ns
14
2,
3
ns
14
4
ms
15,
16
5
+200 mV.
REF
.
TT
1, 2
Max
Unit
Figure
Notes
BCLKs
15
5
BCLKs
15
3
µs
16
4
Table 9
and BCLK,
and
Table 21
for at least 2 µs.
Datasheet