AT89LP216 Atmel Corporation, AT89LP216 Datasheet

Page 1

... MCS-51 instruction set. The AT89LP216 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instruc- tions to execute in 12 clock cycles. In the AT89LP216 CPU, instructions ® 51 Products ...

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... MHz RC oscillator, on-chip crystal oscillator, and a four-level, six-vector interrupt system. The two timer/counters in the AT89LP216 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter. In addition, the timer/counters may independently drive a pulse width modulation output ...

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... SS: SPI slave select input. I GPI4: General-purpose Interrupt input 4. I/O P1.6: User-configurable I/O Port 1 bit 6. I/O MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When configured as slave, this pin 16 P1 output. I GPI6: General-purpose Interrupt input 6. 3621E–MICRO–11/10 AT89LP216 Section 10.3 “External Reset” on page 15) 3 ...

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... Figure 4-1. 5. Comparison to Standard 8051 The AT89LP216 is part of a family of devices with enhanced features that are fully binary com- patible with the MCS-51 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel’s existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051 ...

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... Reset The RST pin of the AT89LP216 is active-low as compared with the active high reset in the stan- dard 8051. In addition, the RST pin is sampled every clock cycle and must be held low for a minimum of two clock cycles, instead of 24 clock cycles recognized as a valid reset. ...

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... Figure 6-1. A map of the AT89LP216 program memory is shown in space from 0000h to 07FFh, the AT89LP216 also supports a 64-byte User Signature Array and a 32-byte Atmel Signature Array that are accessible by the CPU in a read-only fashion. In order to read from the signature arrays, the SIGEN bit in AUXR1 must be set. While SIGEN is one, MOVC A,@A+DPTR will access the signature arrays ...

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... Data Memory The AT89LP216 contains 128 bytes of general SRAM data memory plus 128 bytes of I/O mem- ory mapped into a single 8-bit address space. The 128 bytes of data memory may be accessed through both direct and indirect addressing of the lower 128 byte addresses. The 128 bytes of I/O memory reside in the upper 128 byte address space be accessed through direct addressing and contains the Special Function Registers (SFRs) ...

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... Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 7-1. AT89LP216 SFR Map and Reset Values 8 9 0F8H ...

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... Enhanced CPU The AT89LP216 uses an enhanced 8051 CPU that runs times the speed of standard 8051 devices ( times the speed of X2 8051 devices). The increase in performance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle ...

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... AT89LP216). Violating the physical space limits may cause unknown program behavior. With the CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, and JNZ condi- tional branching instructions, the same previous rule applies ...

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... Clock Source Fuse 1 Fuse Crystal Oscillator Connections 0–10 pF for Crystals = 0–10 pF for Ceramic Resonators R1 = 4–5 MΩ AT89LP216 Table “User Configuration Selected Clock Source Crystal Oscillator Reserved External Clock on XTAL1 Internal 8 MHz RC Oscillator ~10 pF ~10 pF 9-1. No internal 11 ...

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... Figure 9-2. 9.3 Internal RC Oscillator The AT89LP216 has an internal RC oscillator tuned to 8.0 MHz ±1.0% at 5.0V and 25⋅ C. When enabled as the clock source, XTAL1 and XTAL2 may be used as P3.2 and P3.3, respectively. The XTAL2 may also be configured to output a divided version of the system clock. The fre- quency of the oscillator may be adjusted by changing the RC Adjust Fuses. ...

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... During reset, all I/O Registers are set to their initial values, the port pins are tristated, and the program starts execution from the Reset Vector, 0000H. The AT89LP216 has five sources of reset: power-on reset, brown-out reset, external reset, watchdog reset, and software reset. ...

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... Internal Reset Note: The start-up timer delay is user configurable with the Start-up Time User Fuses and depends on the clock source time for V the start-up time after a Brown-out Reset or when waking up from Power-down during internally timed mode. AT89LP216 POR POR ...

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... SUT Fuse 1 10.2 Brown-out Reset The AT89LP216 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD is nomi- nally 2.2V. The purpose of the BOD is to ensure that if V the system will gracefully enter reset without the possibility of errors induced by incorrect execu- tion ...

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... The CPU may generate an internal 16-clock cycle reset pulse by writing the software reset sequence 5AH/A5H to the WDRST register. A software reset will set the SWRST bit in WDT- CON. See 11. Power Saving Modes The AT89LP216 supports two different power-reducing modes: Idle and Power-down. These modes are accessed through the PCON register. 11.1 Idle Mode Setting the IDL bit in PCON enters idle mode ...

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... RST is brought high. Figure 11-3. Reset Recovery from Power-down. PWD XTAL1 RST Internal Clock Internal Reset 3621E–MICRO–11/10 t SUT Figure 11-3. The internal clock will not be allowed Table 10-1 on page 15). If RST returns high before the time-out, t SUT AT89LP216 Figure 17 ...

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... Idle Mode bit. Setting this bit activates Idle mode operation 12. Interrupts The AT89LP216 provides 7 interrupt sources: two external interrupts, two timer interrupts, a serial port interrupt, a general-purpose interrupt, and an analog comparator interrupt. These interrupts and the system reset each have a separate program vector at the start of the program memory space ...

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... Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Port General-purpose Interrupt Analog Comparator 3621E–MICRO–11/10 Interrupt Vector Addresses Source RST or POR or BOD IE0 TF0 IE1 TF1 SPIF GPIF CF AT89LP216 Vector Address 0000H 0003H 000BH 0013H 001BH 0023H 002BH 0033H 19 ...

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... Thus single-interrupt system, the response time is always more than 5 clock cycles and less than 13 clock cycles. See Figure 12-1. Minimum Interrupt Response Time Figure 12-2. Maximum Interrupt Response Time AT89LP216 20 Figures 12-1 and 12-2. Clock Cycles ...

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... External Interrupt 1 Priority Low PT0 Timer 0 Interrupt Priority Low PX0 External Interrupt 0 Priority Low 3621E–MICRO–11/10 EGP ES ET1 PGP PS PT1 AT89LP216 Reset Value = 0000 0000B EX1 ET0 EX0 Reset Value = X000 0000B PX1 PT0 PX0 ...

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... Timer 0 Interrupt Priority High PX0H External Interrupt 0 Priority High 13. I/O Ports The AT89LP216 can be configured for between 11 and 14 I/O pins. The exact number of I/O pins available depends on the clock and reset options as shown in 5V tolerant as inputs, that is they can be pulled up or driven to 5.5V even when operating at a lower V CC lup is required to convert outputs to CMOS levels ...

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... Configuration Modes for Port x, Bit y PxM1.y Port Mode 0 0 Quasi-bidirectional 0 1 Push-pull Output 1 0 Input Only (High Impedance Open-drain Output 1 Clock Delay (D Flip-Flop) AT89LP216 Figure 13-1. The input cir- Figure 13-3 Very Strong Weak Weak Input Data PWD ...

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... DC operation and hot temperature. Under AC operation an inte- grated boost circuit provides more source current. The push-pull port configuration is shown in Figure 13-5. The input circuitry of P1.3, P3.2 and P3.3 is not disabled during Power-down (see Figure 13-3). AT89LP216 24 level and must be taken into consideration. CC Input Data ...

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... Port 1 Analog Functions The AT89LP216 incorporates an analog comparator. In order to give the best analog perfor- mance and minimize power consumption, pins that are being used for analog functions must have both their digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port pins into the input-only mode as described in inputs on P1 ...

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... Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP216 share functionality with the various I/Os needed for the peripheral units. functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a “ ...

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... P3.6 14. Enhanced Timer/Counters The AT89LP216 has two 16-bit Timer/Counter registers: Timer 0 and Timer Timer, the register increase every clock cycle by default. Thus, the register counts clock cycles. Since a clock cycle consists of one oscillator period, the count rate is equal to the oscillator frequency. ...

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... RH1/RL1 and the overflow flag bit in TCON is set. See gives the full 16-bit timer period compatible with the standard 8051. Mode 1 operation is the same for Timer/Counter 0. Figure 14-2. Timer/Counter 1 Mode 1: 16-bit Auto-reload AT89LP216 28 OSC ÷TPS C ...

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... Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP216 can appear to have three Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt ...

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... Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. IE0 Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. IT0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. AT89LP216 30 TF0 TR0 IE1 ...

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... Control Mode Timer 0 low-byte Timer 1 low-byte Timer 0 high-byte Timer 1 high-byte Mode Timer 0 reload low-byte Timer 1 reload low-byte Timer 0 reload high-byte Timer 1 reload high-byte AT89LP216 Reset Value = 0000 0000B C Timer0 Timer 0 gate bit Timer 0 counter/timer select bit Timer 0 M1 bit ...

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... PSC00 14.5 Pulse Width Modulation On the AT89LP216, Timer 0 and Timer 1 may be independently configured as 8-bit asymmetri- cal (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or PWM1EN bits in TCONB, respectively. In PWM Mode the generated waveform is output on the timer's input pin T1. Therefore, C/T must be set to “0” when in PWM mode. and the T0 (P3.4) and T1 (P3.5) must be configured in an output mode ...

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... Timer 0 in PWM Mode 2. 3621E–MICRO–11/ out Mode 0: Duty Cycle % ÷TPS OSC Control TR1 GATE f = out Mode 1: Duty Cycle % Oscillator Frequency ------------------------------------------------------ - Mode × out 2 AT89LP216 Oscillator Frequency 1 × ------------------------------------------------------ - -------------------- - PSC0 + 1 TPS + 1 × 256 2 RH0 × ----------- - 100 = 256 RH1 (8 Bits) TL1 OCR1 ...

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... Figure 14-7. Timer/Counter 1 PWM Mode 1 GATE INT1 Pin Figure 14-8. Timer/Counter 1 PWM Mode 2 Note: Figure 14-9. PWM Mode 2 Waveform AT89LP216 34 ÷TPS OSC Control TR1 ÷TPS OSC Control TR1 GATE INT1 Pin {RH0 & RL0}/{RH1 & RL1} are not required by Timer 0/Timer 1 during PWM Mode 2 and may be used as temporary storage registers ...

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... TH0. PWM Mode 3 is for applications requiring a single PWM channel and two timers, or two PWM channels and an extra timer or counter. With Timer 0 in PWM Mode 3, the AT89LP216 can appear to have three Timer/Counters. When Timer PWM Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3 ...

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... External Interrupts When the AT89LP216 is configured to use the internal RC Oscillator, XTAL1 and XTAL2 may be used as the INT0 and INT1 external interrupt sources. When the external clock source is used, XTAL2 is available as INT1. Neither interrupt is available in crystal oscillator mode.The external interrupts can be programmed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON ...

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... P1.x active. Must be cleared by software. 3621E–MICRO–11/10 GPLS5 GPLS4 GPLS3 GPIEN5 GPIEN4 GPIEN3 GPIF5 GPIF4 GPIF3 AT89LP216 Reset Value = 0000 0000B GPLS2 GPLS1 GPLS0 Reset Value = 0000 0000B GPIEN2 GPIEN1 GPIEN0 Reset Value = 0000 0000B GPIF2 GPIF1 GPIF0 2 ...

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... Serial Interface The serial interface on the AT89LP216 implements a Universal Asynchronous Receiver/Trans- mitter (UART). The UART has the following features: • Full Duplex Operation • Data Bits • Framing Error Detection • Multiprocessor Communication Mode with Automatic Address Recognition • Baud Rate Generator Using Timer 1 • ...

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... TB8 5 4 SM1 Mode Description 0 0 shift register 1 1 8-bit UART 0 2 9-bit UART 1 3 9-bit UART AT89LP216 See “Automatic Address Recognition” on page 48. Reset Value = 0000 0000B RB8 (2) Baud Rate f /2 osc variable (Timer /16 osc ...

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... Programmers can achieve very low baud rates with Timer 1 by configuring the Timer to run as a 16-bit auto-reload timer (high nibble of TMOD = 0001B). In this case, the baud rate is given by the following formula. Table 18-1 AT89LP216 40 Mode 0 Baud Rate SMOD1 2 ...

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... Commonly Used Baud Rates Generated by Timer 1 (TPS = 0000B) f (MHz) OSC 11.059 9.6K 11.059 4.8K 11.059 2.4K 11.059 1.2K 11.059 137.5 11.986 110 6 110 12 shows a simplified functional diagram of the serial port in Mode 0 and associ- AT89LP216 Timer 1 SMOD1 C/T Mode ...

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... Figure 18-1. Serial Port Mode 0 1/2 f osc WRITE TO SBUF SEND SHIFT RXD (DATA OUT) TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD (DATA IN) TXD (SHIFT CLOCK) AT89LP216 42 INTERNAL BUS “1“ INTERNAL BUS 3621E–MICRO–11/10 ...

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... Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the AT89LP216, the baud rate is determined by the Timer 1 overflow rate. plified functional diagram of the serial port in Mode 1 and associated timings for transmit and receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The “ ...

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... DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 TXD START BIT TI ÷16 RESET RX CLOCK RXD START BIT BIT DETECTOR SAMPLE TIMES SHIFT RI AT89LP216 44 INTERNAL BUS “1” SBUF CL ZERO DETECTOR SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND TI TI SERIAL PORT ÷ ...

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... RXD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI. 3621E–MICRO–11/10 show a functional diagram of the serial port in Modes 2 and 3. The and Either SM2 = 0 or the received 9th data bit = 1 AT89LP216 45 ...

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... Figure 18-3. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 AT89LP216 46 INTERNAL BUS INTERNAL BUS 3621E–MICRO–11/10 ...

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... RX CLOCK SEND TI SERIAL PORT ÷16 LOAD RX CLOCK RI SBUF START RX CONTROL SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG. (9 BITS) LOAD SBUF SBUF READ SBUF INTERNAL BUS AT89LP216 TXD SHIFT D6 D7 TB8 STOP BIT RB8 STOP BIT 47 ...

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... A unique address for slave 1 would be 1100 0001 since a “1” in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit (for slave 0) and bit (for slave 1). Thus, both could be addressed with 1100 0000. AT89LP216 48 SADDR = 1100 0000 ...

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... UART drivers which do not make use of this feature. 19. Serial Peripheral Interface The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the AT89LP216 and peripheral devices or between multiple AT89LP216 devices. The SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • ...

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... SPI immediately loads the buffered byte into the shift register, resets WCOL, and continues transmission without stopping and restarting the clock generator. As long as the CPU can keep the write buffer full in this manner, multiple bytes may be transferred with minimal latency between bytes. AT89LP216 50 Master MSB ...

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... SPD7 SPD6 Bit 7 6 3621E–MICRO–11/10 DORD MSTR CPOL SPD5 SPD4 SPD3 AT89LP216 Reset Value = 0000 0000B CPHA SPR1 SPR0 follows: OSC. Reset Value = 00H (after cold reset) unchanged (after warm reset) SPD2 SPD1 SPD0 ...

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... DISSO bit. Enhanced SPI mode select bit. When ENH = 0, SPI is in normal mode, i.e. without write double buffering. ENH When ENH = 1, SPI is in enhanced mode with write double buffering. The Tx buffer shares the same address with the SPDR register. AT89LP216 52 LDEN – – ...

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... LATCH CLK Oscillator MSB Divider ÷4÷8÷32÷64 SPI Clock (Mater) Select MSTR SPE SPI Control 8 SPI Status Register 8 SPI Interrupt Internal Request Data Bus AT89LP216 7 Serial Slave 2:1 D MUX LATCH CLK Parallel Slave (Read Buffer LATCH CLK LSB ...

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... Figure 19-5. SPI Transfer Format with CPHA = 1 SCK CYCLE # (FOR REFERENCE) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) Note: *Not defined but normally LSB of previously transmitted character. AT89LP216 54 19-5. To prevent glitches on SCK from disrupting the interface, CPHA, CPOL MSB ...

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... Analog Comparator A single analog comparator is provided on the AT89LP216. The analog comparator has the fol- lowing features: • Comparator Output Flag and Interrupt • Selectable Interrupt Condition – High- or Low-level – Rising- or Falling-edge – Output Toggle • Hardware Debouncing Modes Comparator operation is such that the output is a logic “1” when the positive input AIN0 (P1.0]) is greater than the negative input AIN1 (P1 ...

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... Note: 1. Debouncing modes require the use of Timer 1 to generate the sampling delay. Figure 20-1. Negative Edge with Debouncing Example Comparator Out Timer 1 Overflow AT89LP216 56 CIDL CF CEN Interrupt Mode Negative (Low) level Positive edge (1) Toggle with debouncing (1) Positive edge with debouncing ...

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... PS1 The WDT time-out period is dependent on the system clock frequency. ------------------------------------------------------ - Time-out Period = Oscillator Frequency MOV WDTRST, #01Eh MOV WDTRST, #0E1h AT89LP216 (1) Period PS0 (Clock Cycles) 0 16K 1 32K 0 64K 1 128K 0 256K 1 512K 0 1024K 1 2048K ( ) PS ...

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... Software Reset A Software Reset of the AT89LP216 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will set the SWRST flag in WDTCON. However any time an incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or 5AH/A5H), a software reset will immediately be generated and both the SWRST and WDTOVF flags will be set ...

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... The AT89LP216 is fully binary compatible with the MCS-51 instruction set. The difference between the AT89LP216 and the standard 8051 is the number of cycles required to execute an instruction. Instructions in the AT89LP216 may take clock cycles to complete. The execution times of most instructions may be computed using Table 22-1 ...

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... ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data RL A RLC RRC A SWAP A AT89LP216 60 Instruction Execution Times and Exceptions (Continued) Bytes ...

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... Instruction Execution Times and Exceptions (Continued) Bytes AT89LP216 Clock Cycles 8051 AT89LP Hex Code 12 1 E8- E6- F8- A8- 78- ...

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... RETI AJMP addr11 LJMP addr16 JMP @A+DPTR JMP @A+PC CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP (1) BREAK Note: AT89LP216 62 Instruction Execution Times and Exceptions (Continued) Bytes ...

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... On-chip Debug System The AT89LP216 On-chip Debug (OCD) System uses a two-wire serial interface to control pro- gram flow; read, modify, and write the system state; and program the nonvolatile memory. The OCD System has the following features: • Complete program flow control • ...

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... XTAL1/P3.2. The INT0, INT1 and CLKOUT functions cannot be emulated in this mode. • The AT89LP216 does not support In-Application Programming and therefore the device must be reset before changing the program code during debugging. This includes the insertion/deletion of software breakpoints. ...

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... The ISP interface uses the SPI clock mode 0 (CPOL = 0,CPHA = 0) exclusively with a maximum frequency of 5 MHz. • The AT89LP216 will enter programming mode only when its reset line (RST) is active (low). To simplify this operation recommended that the target reset can be controlled by the In- System programmer ...

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... Fuse is disabled, ISP may only be entered at POR. 24.2 Memory Organization The AT89LP216 offers 2K bytes of In-System Programmable (ISP) nonvolatile Flash code mem- ory. In addition, the device contains a 64-byte User Signature Array and a 32-byte read-only Atmel Signature Array. The memory organization is shown in memory is divided into pages of 32 bytes each. A single read or write command may only access a single page in the memory ...

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... Page oriented instructions always include a full 16-bit address. The higher order bits select the page and the lower order bits select the byte within that page. The AT89LP216 allocates 5 bits for byte address and 6 bits for page address. The page to be accessed is always fixed by the page address as transmitted ...

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... Figure 24-3. Command Sequence Flow Chart Figure 24-4. ISP Command Packet SS SCK MOSI Preamble 1 MISO X AT89LP216 68 Input Preamble 1 (AAh) Input Preamble 2 (55h) Input Opcode Input Address High Byte Input Address Low Byte Input/Output Address +1 Data Preamble 2 ...

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... Fuse definitions. for Lock Bit definitions. 00H = 1EH 01H = 29H 02H = FFH AT89LP216 Addr Low Data 0 – – – – – xxxx xxxx Status Out xxxb bbbb DataIn 0 ... DataIn n aaab bbbb DataIn 0 ...

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... Flash Security The AT89LP216 provides two Lock Bits for Flash Code Memory security. Lock bits can be left unprogrammed (FFh) or programmed (00h) to obtain the protection levels listed in Lock bits can only be erased (set to FFh) by Chip Erase. Lock bit mode 2 disables programming of all memory spaces, including the User Signature Array and User Configuration Fuses ...

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... User Configuration Fuses The AT89LP216 includes 19 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row as listed in ming 00h to their locations. Programming FFh to fuse location will cause that fuse to maintain its previous state. To set a fuse (set to FFh) the fuse row must be erased and then reprogrammed using the Fuse Write with Auto-erase command ...

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... Drive SCK low. 2. Wait at least t 3. Tristate MOSI. 4. Wait at least t 5. Wait no more than t Figure 24-6. Serial Programming Power-down Sequence V RST SCK MISO MOSI AT89LP216 72 75. 15). . and drive SS high. PWRUP for the internal Power-on Reset to complete. The value of t SUT PWRUP ...

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... SS high. SSD and bring RST high. SSZ and tristate SS. RHZ V CC XTAL1 RST t SS SSZ t SSD SCK MISO MOSI The waveforms on this page are not to scale. AT89LP216 t RLZ t t STL ZSS t SSE HIGH Z HIGH Z t RHZ HIGH Z HIGH Z 73 ...

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... CPHA = 0) where bits are sampled on the rising edge of SCK and output on the falling edge of SCK. For more detailed timing information see Figure 24-9. ISP Byte Sequence Figure 24-10. Serial Programming Interface Timing SCK MISO MOSI AT89LP216 74 Figure 24-9. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0, SCK MOSI 7 ...

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... Output Disable Time SS Enable Lead Time SS Disable Lag Time SCK Setup to SS Low SCK Hold after SS High Write Cycle Time Write Cycle with Auto-Erase Time Chip Erase Cycle Time independent SCK CLCL AT89LP216 24-6, Figure 24-7, Figure 24-8, and Min Max 100 1 ...

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... If I exceeds the test condition than the listed test conditions levels are listed for DC operation. Under AC conditions a boost circuit provides additional source current. OH1 3. Minimum V for Power-down is 2V. CC AT89LP216 76 *NOTICE: Condition (Ports mA 85° ± 10 -80 µ ...

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... Supply Current (Internal Oscillator) Figure 25-1. Active Supply Current vs. VCC ( 8MHz Internal Oscillator) Figure 25-2. Idle Supply Current vs. Vcc (8 MHz Internal Oscillator) 3621E–MICRO–11/ 2.0 2.5 3.0 3.5 Vcc (V) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 Vcc (V) AT89LP216 4.0 4.5 5.0 5.5 4.0 4.5 5.0 5.5 85C -40C 25C 85C -40C 25C 77 ...

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... Supply Current (External Clock) Figure 25-3. Active Supply Current vs. Frequency Figure 25-4. Idle Supply Current vs. Frequency AT89LP216 Frequency (MHz Frequency (MHz 3621E–MICRO–11/10 5.5V 5.0V 4.5V 3.6V 3.0V 2.4V 5.5V 5.0V 4.5V 3.3V 2.7V 2.4V ...

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... V = 2.4–5. -40–85° 4.5–5. -40–85° 2.4–3. 0–70° 2.4–5. 0–70° 4.5–5. 0–70° 2.4–3. AT89LP216 4.0 4.5 5.0 5.5 Min Max ±4 ±3 ±3 ±3 ±2 ±2 7.8 8.4 7.8 8.2 8.0 8.4 7.8 8.3 7.8 8.1 8.0 8.3 -40C 0C 25C 70C ...

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... Quasi-Bidirectional Output Figure 25-6. Quasi-Bidirectional Output I-V Characteristic at 5V Figure 25-7. Quasi-Bidirectional Output I-V Characteristic at 3V AT89LP216 80 2.0 2.5 3.0 3.5 0 -20 -40 -60 -80 -100 V OH 0.0 0.5 1.0 1.5 -10 -20 -30 -40 -50 -60 -70 - 4.0 4.5 5.0 (V) 2.0 2.5 3.0 (V) 85C -40C 25C 85C -40C 25C 3621E–MICRO–11/10 ...

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... Under DC operating conditions the Push-Pull Outputs exhibit reduced V atures due to the 5V tolerant port structure. Under AC conditions a boost circuit provides additional source current. If additional DC source current is required pull-ups may be needed. DC conditions are most likely to exist when the device enters Power- down mode. AT89LP216 (V) 1 ...

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... Crystal Oscillator Figure 25-10. Quartz Crystal Input at 5V Figure 25-11. Ceramic Resonator Input at 5V AT89LP216 82 Oscillator Amplitude vs. Frequency Quartz Crystal with R1 = 4MΩ Frequency (MHz) Oscillator Amplitude vs. Frequency Ceramic Resonator with R1 = 4MΩ Frequency (MHz) ...

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... External Clock Fall Time CHCL Table 25-3. Clock Characteristics Symbol Parameter f Crystal Oscillator Frequency XTAL f Internal Oscillator Frequency IRC 3621E–MICRO–11/10 Condition T = 25° 5. 2.4V to 5.5V CC AT89LP216 Min Max Units 0 20 MHz Min Max Units 0 20 MHz 7 ...

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... SIH t Serial Output Hold Time SOH t Serial Output Valid Time SOV t Output Enable Time SOE t Output Disable Time SOX t Slave Enable Lead Time SSE t Slave Disable Lag Time SSD AT89LP216 84 Min Max 41.6 4t CLCL SCK SCK Min Max 41 ...

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... MOSI 3621E–MICRO–11/ SCK t t SHSL SLSH t t SLSH SHSL t t SOH SOV SCK SSE t t SHSL SLSH t t SLSH SHSL SOV SOH SOE AT89LP216 SIS SIH t t SSD SF t SOX t t SIS SIH 85 ...

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... Figure 25-15. SPI Master Timing (CPHA = 1) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI Figure 25-16. SPI Slave Timing (CPHA = 1) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI AT89LP216 SOV 3621E–MICRO–11/10 ...

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... Valid Valid Valid (1) - 0.5V for a logic “1” and 0.45V for a logic “0”. Timing measurements are made at CC max. for a logic “0” level occurs AT89LP216 Variable Oscillator Min Max 2t -15 CLCL t -15 CLCL t -15 CLCL ...

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... Test Condition, Active Mode, All Other Pins are Disconnected CC 25.7.4 I Test Condition, Idle Mode, All Other Pins are Disconnected CC 25.7.5 Clock Signal Waveform for 0.5V CC 0.45V 25.7.6 I Test Condition, Power-down Mode, All Other Pins are Disconnected AT89LP216 RST (NC) XTAL2 CLOCK SIGNAL XTAL1 RST CC (NC) XTAL2 ...

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... Wide, Plastic Gull Wing Small Outline (SOIC) 16X 16-lead, 0.173” Wide, Plastic Thin Shrink Small Outline Package (TSSOP) 3621E–MICRO–11/10 Ordering Code AT89LP216-20PU AT89LP216-20SU AT89LP216-20XU Package Type AT89LP216 Package Operation Range 16P3 Industrial 16S (-40⋅ 85⋅ C) 16X 89 ...

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... PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-001, Variation AB. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89LP216 90 D PIN ...

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... L is the length of the terminal for soldering to a substrate. 2325 Orchard Parkway San Jose, CA 95131 R 3621E–MICRO–11/ TITLE 16S, 16-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) AT89LP216 E End View L C COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM MAX A 2.35 – ...

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... TSSOP Top View e D Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153-AB. 2325 Orchard Parkway San Jose, CA 95131 R AT89LP216 SYMBOL A1 A1 TITLE 16X, 16-lead, 4.4 mm Body Width, Plastic Thin Shrink ...

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... Updated Clock Parameters on page 83 • Removed Standard Packaging Offering • Replaced C1 with R1 in oscillator diagram • Added oscillator input characteristics on • Noted output levels as TTL. See AT89LP216 Figure 9-1 on page 11 Figure 9-2 on page 12 Figure 19-1 on page 50 page 71 page 71 page 77 page 79 page 80 Figure 9-1 on page 11. ...

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... AT89LP216 94 3621E–MICRO–11/10 ...

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... System Clock .....................................................................................................4 5.2 Instruction Execution with Single-cycle Fetch ...................................................4 5.3 Interrupt Handling ..............................................................................................5 5.4 Timer/Counters ..................................................................................................5 5.5 Serial Port ..........................................................................................................5 5.6 Watchdog Timer ................................................................................................5 5.7 I/O Ports ............................................................................................................5 5.8 Reset .................................................................................................................5 6.1 Program Memory ...............................................................................................6 6.2 Data Memory .....................................................................................................7 8.1 Restrictions on Certain Instructions .................................................................10 9.1 Crystal Oscillator .............................................................................................11 9.2 External Clock Source .....................................................................................12 9.3 Internal RC Oscillator ......................................................................................12 9.4 System Clock Out ............................................................................................12 10.1 Power-on Reset ...............................................................................................13 10.2 Brown-out Reset ..............................................................................................15 10.3 External Reset .................................................................................................15 10.4 Watchdog Reset ..............................................................................................16 AT89LP216 i ...

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... Table of Contents (Continued) 11 Power Saving Modes ............................................................................. 16 12 Interrupts ................................................................................................ 18 13 I/O Ports .................................................................................................. 22 14 Enhanced Timer/Counters .................................................................... 27 15 External Interrupts ................................................................................. 36 16 General-purpose Interrupts .................................................................. 36 17 Serial Interface ....................................................................................... 38 18 Baud Rates ............................................................................................. 40 19 Serial Peripheral Interface ..................................................................... 49 20 Analog Comparator ............................................................................... 55 AT89LP216 ii 10.5 Software Reset ................................................................................................16 11.1 Idle Mode .........................................................................................................16 11.2 Power-down Mode ...........................................................................................16 12.1 Interrupt Response Time .................................................................................20 13.1 Port Configuration ...

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... Programming Interface Timing ........................................................................72 25.1 Absolute Maximum Ratings* ...........................................................................76 25.2 DC Characteristics ...........................................................................................76 25.3 Typical Characteristics ....................................................................................77 25.4 Clock Characteristics .......................................................................................83 25.5 Serial Peripheral Interface Timing ..................................................................84 25.6 Serial Port Timing: Shift Register Mode Test Conditions ................................87 25.7 Test Conditions ................................................................................................87 26.1 Green Package Option (Pb/Halide-free) ..........................................................89 27.1 16P3 – PDIP ....................................................................................................90 27.2 16S – SOIC .....................................................................................................91 27.3 16X – TSSOP ..................................................................................................92 AT89LP216 iii ...

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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...