AT89LP428 Atmel Corporation, AT89LP428 Datasheet - Page 94

• Manufacturer Part Number: AT89LP428
• Manufacturer: Atmel Corporation

Specifications of AT89LP428

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 512
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

While the TXE flag is set, the transmit buffer is empty. TXE can be cleared by software or by
writing to SPDR. Writing to SPDR will clear TXE and load the transmit buffer. The user may load
the buffer while the shift register is busy, i.e. before the current transfer completes. When the
current transfer completes, the queued byte in the transmit buffer is moved to the shift register
and the next transfer commences. TXE will generate an interrupt if the SPI interrupt is enabled
and if the ENH bit in SPSR is set. For multi-byte transfers, TXE may be used to remove any
dead time between byte transmissions.
The SPI master can operate in two modes: multi-master mode and single-master mode. By
default, multi-master mode is active when SSIG = 0. In this mode, the SS input is used to dis-
able a master device when another master is accessing the bus. When SS is driven low, the
master device becomes a slave by clearing its MSTR bit and a Mode Fault is generated by set-
ting the MODF bit in SPSR. MODF will generate an interrupt if enabled. The MSTR bit must be
set in software before the device may become a master again. Single-master mode is enabled
by setting SSIG = 1. In this mode SS is ignored and the master is always active. SS may be
used as a general-purpose I/O in this mode.
17.2
Slave Operation
When the AT89LP428/828 is not configured for master operation, MSTR = 0, it will operate as
an SPI slave. In slave mode, bytes are shifted in through MOSI and out through MISO by a mas-
ter device controlling the serial clock on SCK. When a byte has been transferred, the SPIF flag
is set to “1” and an interrupt request is generated, if enabled. The data received from the
addressed master device is also transferred from the shift register to the receive buffer. The
received data is accessed by reading SPDR. A slave device cannot initiate transfers. Data to be
transferred to the master device must be preloaded by writing to SPDR. Writes to SPDR are
double-buffered. The transmit buffer is loaded first and if the shift register is empty, the contents
of the buffer will be transferred to the shift register.
While the TXE flag is set, the transmit buffer is empty. TXE can be cleared by software or by
writing to SPDR. Writing to SPDR will clear TXE and load the transmit buffer. The user may load
the buffer while the shift register is busy, i.e. before the current transfer completes. When the
current transfer completes, the queued byte in the transmit buffer is moved to the shift register
and waits for the master to initiate another transfer. TXE will generate an interrupt if the SPI
interrupt is enabled and if the ENH bit in SPSR is set.
The SPI slave can operate in two modes: 4-wire mode and 3-wire mode. By default, 4-wire
mode is active when SSIG = 0. In this mode, the SS input is used to enable/disable the slave
device when addressed by a master. When SS is driven low, the slave device is enabled and will
shift out data on MISO in response to the serial clock on SCK. While SS is high, the SPI slave
will remain sleeping with MISO inactive. 3-wire mode is enabled by setting SSIG = 1. In this
mode SS is ignored and the slave is always active. SS may be used as a general-purpose I/O in
this mode.
The Disable Slave Output bit, DISSO in SPSR, may be used to disable the MISO line of a slave
device. DISSO can allow several slave devices to share MISO while operating in 3-wire mode. In
this case some protocol other than SS may be used to determine which slave is enabled.
AT89LP428/828
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