AT89LP51ID2 Atmel Corporation, AT89LP51ID2 Datasheet - Page 61

• Manufacturer Part Number: AT89LP51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

9. Interrupts
9.1
3714A–MICRO–7/11
Interrupt Priority
The AT89LP51RD2/ED2/ID2 provides 11 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (Timers 0, 1 and 2), a serial port interrupt, an SPI interrupt, a key-
board interrupt, a PCA interrupt, an analog comparator interrupt and an ADC interrupt. These
interrupts and the system reset each have a separate program vector at the start of the program
memory space.
Table 9-1.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the
interrupt enable registers: IEN0 and IEN1. The IEN0 register also contains a global disable bit,
EA, which disables all interrupts. All of the bits that generate interrupts can be set or cleared by
software, with the same result as though they had been set or cleared by hardware. That is,
interrupts can be generated and pending interrupts can be canceled in software.
Each interrupt source can be individually programmed to one of four priority levels by setting or
clearing bits in the interrupt priority registers: IPL0, IPL1, IPH0 and IPH1. IPL0 and IPL1 hold the
low order priority bits and IPH0 and IPH1 hold the high priority bits for each interrupt as shown in
Table
rupt, but not by another interrupt of the same or lower priority. The highest priority interrupt
cannot be interrupted by any other interrupt source. If two requests of different priority levels are
pending at the end of an instruction, the request of higher priority level is serviced. If requests of
the same priority level are pending at the end of an instruction, an internal polling sequence
determines which request is serviced. The polling sequence is based on the vector address; an
interrupt with a lower vector address has higher priority than an interrupt with a higher vector
address, except in the case of the PCA, whose polling priority is moved up by two as shown in
Table 9-1
requests of the same priority level.
Priority
Polling
10
11
12
13
0
1
2
3
4
6
7
5
8
9
9-2. An interrupt service routine in progress can be interrupted by a higher priority inter-
and
Interrupt
System Reset
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port Interrupt
Timer 2 Interrupt
PCA Interrupt
Keyboard Interrupt
Two-Wire Interrupt
SPI Interrupt
reserved
Analog Comparator Interrupt
ADC Interrupt
Interrupt Vector Addresses and Priority
Figure
9-1. Note that the polling sequence is only used to resolve pending
AT89LP51RD2/ED2/ID2 Preliminary
Source
RST or POR or BOD
TF0
TF1
KBF
IE0
IE1
RI or TI
TF2 or EXF2
CF, CCF0, CCF1, CCF2, CCF3 or CCF4
SI
SPIF or MODF or TXE
CFA or CFB
ADIF
7-0
Address
Vector
000BH
001BH
002BH
003BH
004BH
005BH
0000H
0003H
0013H
0023H
0033H
0043H
0053H
0063H
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