AT89LP51RC2 Atmel Corporation, AT89LP51RC2 Datasheet - Page 10

• Manufacturer Part Number: AT89LP51RC2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RC2

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 1.375
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
10
AT89LP51RB2/RC2/IC2 Summary
Timer/Counters
Interrupt Handling
Keyboard Interface
Serial Port
I/O Ports
A common prescaler is available to divide the time base for Timer 0, Timer 1, Timer 2 and the
WDT. The TPS
defaults to 0101B, which causes the timers to count once every machine cycle. The counting
rate can be adjusted linearly from the system clock rate to 1/16 of the system clock rate by
changing TPS
affect Timer 2 in Clock Out or Baud Generator modes.
In Compatibility mode the sampling of the external Timer/Counter pins: T0, T1, T2 and T2EX;
and the external interrupt pins, INT0 and INT1, is also controlled by the prescaler. In Fast mode
these pins are always sampled at the system clock rate.
Both Timer 0 and Timer 1 can toggle their respective counter pins, T0 and T1, when they over-
flow by setting the output enable bits in TCONB.
Fast mode allows for faster interrupt response due to the shorter instruction execution times.
The AT89LP51RB2/RC2/IC2 does not clear the keyboard flag register (KBF) after a read. Each
bit must be cleared in software. This allows the interrupt to be generate once per flag when mul-
tiple flags are set, if desired. To mimic the old behavior the service routine must clear the whole
register.
The keyboard can also support general edge-triggered interrupts with the addition of the
KBMOD register.
The timer prescaler increases the range of achievable baud rates when using Timer 1 to gener-
ate the baud rate in UART Modes 1 or 3, including an increase in the maximum baud rate
available in Compatibility mode. Additional features include automatic address recognition and
framing error detection.
The shift register mode (Mode 0) has been enhanced with more control of the polarity, phase
and frequency of the clock and full-duplex operation. This allows emulation of master serial
peripheral (SPI) and two-wire (TWI) interfaces.
The P0, P1, P2 and P3 I/O ports of the AT89LP51RB2/RC2/IC2 may be configured in four differ-
ent modes. The default setting depends on the Tristate-Port User Fuse. When the fuse is set all
the I/O ports revert to input-only (tristated) mode at power-up or reset. When the fuse is not
active, ports P1, P2 and P3 start in quasi-bidirectional mode and P0 starts in open-drain mode.
P4 always operates in quasi-bidirectional mode. P0 can be configured to have internal pull-ups
by placing it in quasi-bidirectional or output modes. This can reduce system cost by removing
the need for external pull-ups on Port 0.
The P4.4–P4.7 pins are additional I/Os that replace the normally dedicated ALE, PSEN, XTAL1
and XTAL2 pins of the AT89C51RB2/RC2/IC2. These pins can be used as additional I/Os
depending on the configuration of the clock and external memory.
3-0
3-0
. In Fast mode TPS
bits in the CLKREG SFR control the prescaler. In Compatibility mode TPS
3-0
defaults to 0000B, or the system clock rate. TPS does not
3722AS–MICRO–10/11
3-0