ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 150

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.5
8151H–AVR–02/11
Output Compare Unit
Figure 17-2. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clk
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR2). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the output compare output
OC2. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page
The Timer/Counter overflow (TOV2) flag is set according to the mode of operation selected by
the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the
output compare flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1 and global inter-
rupt flag in SREG is set), the output compare flag generates an output compare interrupt. The
OCF2 flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 flag
can be cleared by software by writing a logical one to its I/O bit location. The waveform genera-
tor uses the match signal to generate an output according to operating mode set by the
WGM21:0 bits and compare output mode (COM21:0) bits. The max and bottom signals are used
by the waveform generator for handling the special cases of the extreme values in some modes
count
direction
clear
clk
top
bottom
Tn
DATA BUS
T2
TCNTn
is present or not. A CPU write overrides (has priority over) all counter clear or
T2
). clk
direction
Increment or decrement TCNT2 by 1.
Select between increment and decrement.
Clear TCNT2 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT2 has reached maximum value.
Signalize that TCNT2 has reached minimum value (zero).
153.
T2
count
clear
bottom
can be generated from an external or internal clock source,
Control Logic
top
TOVn
(Int.Req.)
clk
Tn
( From Prescaler )
Clock Select
Detector
Edge
T0
ATmega128A
in the following.
Tn
150