ATmega8535 Atmel Corporation, ATmega8535 Datasheet - Page 183

• Manufacturer Part Number: ATmega8535
• Manufacturer: Atmel Corporation

Specifications of ATmega8535

• Flash (kbytes): 8 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

TWI Status Register – TWSR
TWI Data Register – TWDR
TWI (Slave) Address Register
– TWAR
2502K–AVR–10/06
• Bits 7..3 – TWS: TWI Status
These five bits reflect the status of the TWI logic and the Two-wire Serial Bus. The dif-
ferent status codes are described later in this section. Note that the value read from
TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application
designer should mask the prescaler bits to zero when checking the status bits. This
makes status checking independent of prescaler setting. This approach is used in this
datasheet, unless otherwise noted.
• Bit 2 – Res: Reserved bit
This bit is reserved and will always read as zero.
• Bits 1..0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 74. TWI Bit Rate Prescaler
To calculate bit rates, see “Bit Rate Generator Unit” on page 180. The value of
TWPS1..0 is used in the equation.
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the
TWDR contains the last byte received. It is writable while the TWI is not in the process of
shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware.
Note that the Data Register cannot be initialized by the user before the first interrupt
occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted
out, data on the bus is simultaneously shifted in. TWDR always contains the last byte
present on the bus, except after a wake-up from a sleep mode by the TWI interrupt. In
this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no
data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled
automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7..0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte
received on the Two-wire Serial Bus.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
TWPS1
0
0
1
1
TWS7
TWD7
TWA6
R/W
R
7
1
7
1
7
TWD6
TWS6
TWA5
R/W
R
6
1
TWPS0
0
1
0
1
6
1
6
TWS5
TWD5
TWA4
R/W
R
5
1
5
1
5
TWS4
TWD4
TWA3
R/W
R
4
1
4
1
4
TWS3
Prescaler Value
1
4
16
64
TWD3
TWA2
R/W
3
R
1
3
1
3
TWD2
TWA1
R/W
R
2
–
0
2
1
2
ATmega8535(L)
TWPS1
TWD1
TWA0
R/W
R/W
1
0
1
1
1
TWGCE
TWPS0
TWD0
R/W
R/W
0
0
0
1
0
TWSR
TWDR
TWAR
183