ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 23

• Manufacturer Part Number: ATxmega128A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A3U

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.7
4.8
4.8.1
4.9
4.10
8331A–AVR–07/11
EEPROM
I/O Memory
External Memory
Data Memory and Bus Arbitration
General Purpose I/O Registers
XMEGA AU devices ha EEPROM for nonvolatile data storage. It is addressable in a separate
data space (default) or memory mapped and accessed in normal data space. The EEPROM
supports both byte and page access. Memory mapped EEPROM allows highly efficient
EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is accessible using
load and store instructions. Memory mapped EEPROM will always start at hexadecimal address
0x1000.
The status and configuration registers for peripherals and modules, including the CPU, are
addressable through I/O memory locations. All I/O locations can be accessed by the load
(LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between
the 32 registers in the register file and the I/O memory. The IN and OUT instructions can
address I/O memory locations in the range of 0x00 0x3F directly. In the address range 0x00 -
0x1F, single-cycle instructions for manipulation and checking of individual bits are available.
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These reg-
isters can be used for storing global variables and flags, as they are directly bit-accessible using
the SBI, CBI, SBIS, and SBIC instructions.
Four ports dedicated to external memory, supporting external SRAM, SDRAM, and memory
mapped peripherals such as LCD displays. For details, refer to
page
Since the data memory is organized as four separate sets of memories, the different bus mas-
ters (CPU, DMA controller read and DMA controller write, etc.) can access different memories at
the same time. As
the DMA controller is transferring data from internal SRAM to I/O memory. The USB module acts
as a bus master and is connected directly to internal SRAM through a pseudo-dualport (PDP)
interface.
331. The external memory address space will always start at the end of internal SRAM.
Figure 4-3 on page 24
shows, the CPU can access the external memory while
Atmel AVR XMEGA AU
”EBI - External Bus Interface” on
23