ATxmega128A4U Atmel Corporation, ATxmega128A4U Datasheet - Page 65

• Manufacturer Part Number: ATxmega128A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.14.5
5.14.6
8331A–AVR–07/11
TRFCNTL – DMA Channel Block Transfer Count Register L
TRFCNTH – DMA Channel Block Transfer Count Register H
Table 5-12.
Note:
Table 5-13.
The group configuration is the “base_offset;” for example, TCC1_CCA for the timer/counter C1
CC channel A the transfer trigger.
The TRFCNTH and TRFCNTL register pair represents the 16-bit value TRFCNT. TRFCNT
defines the number of bytes in a block transfer. The value of TRFCNT is decremented after each
byte read by the DMA channel. When TRFCNT reaches zero, the register is reloaded with the
last value written to it.
• Bit 7:0 – TRFCNT[7:0]: DMA Channel n Block Transfer Count Register Low byte
These bits hold the LSB of the 16-bit block transfer count.
The default value of this register is 0x1. If a user writes 0x0 to this register and fires a DMA trig-
ger, DMA will be doing 0xFFFF transfers.
Reading and writing 16-bit values requires special attention. For details, refer to
bit Registers” on page
Bit
+0x05
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
TRGSRC Offset Value
TRGSRC Offset Value
1. CC channel C and D triggers are available only for timer/counters 0.
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
0x00
0x01
R/W
R/W
DMA trigger source offset values for timer/ counter triggers.
DMA trigger source offset values for USART triggers.
7
0
7
1
12.
R/W
R/W
6
1
6
0
Group Configuration
Group Configuration
R/W
R/W
5
1
5
0
CCC
CCD
ERR
CCA
CCB
RXC
DRE
OVF
(1)
(1)
R/W
R/W
4
1
4
0
TRFCNT[15:8]
TRFCNT[7:0]
Description
Overflow/underflow
Error
Compare or capture channel A
Compare or capture channel B
Compare or capture channel C
Compare or capture channel D
Description
Receive complete
Data register empty
R/W
R/W
Atmel AVR XMEGA AU
3
1
3
0
R/W
R/W
2
1
2
0
R/W
R/W
1
1
1
0
R/W
R/W
0
1
0
0
”Accessing 16-
TRFCNTL
TRFCNTH
65