ATxmega32A4 Atmel Corporation, ATxmega32A4 Datasheet
ATxmega32A4
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ATxmega32A4 Summary of contents
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... Board control Networking • • White Goods Optical ® ® ™ AVR XMEGA Microcontroller 2 C and SMBus compatible) • Hand-held battery applications • Power tools • HVAC • Metering • Medical Applications 8/16-bit XMEGA A4 Microcontroller ATxmega128A4 ATxmega64A4 ATxmega32A4 ATxmega16A4 8069Q–AVR–12/10 ...
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... ATxmega64A4- ATxmega32A4- ATxmega16A4- ATxmega32A4- ATxmega16A4- Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green ...
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Pinout/Block Diagram Figure 2-1. Bock Diagram and TQFP/QFN pinout INDEX CORNER PA5 1 PA6 2 PA7 3 PB0 4 PB1 5 PB2 6 PB3 7 GND 8 VCC 9 PC0 10 PC1 11 Notes: 1. For full details on ...
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Figure 2-2. VFBGA pinout Top view Table 2-1. VFBGA pinout 1 A PA3 B PA4 C PA5 D PB1 E GND F VCC G PC1 8069Q–AVR–12/ ...
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Overview The Atmel CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the XMEGA A4 achieves throughputs approaching 1 Million Instructions Per Second (MIPS) per MHz allowing the system ...
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Block Diagram Figure 3-1. XMEGA A4 Block Diagram PA[0..7] PORT A (8) ACA ADCA AREFA VCC/10 Int. Ref. Tempref AREFB PB[0..3] PORT B (4) DACB IRCOM 8069Q–AVR–12/10 PR[0..1] XTAL1/ TOSC1 XTAL2/ TOSC2 Oscillator Circuits/ Clock PORT R (2) Generation ...
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Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading • Atmel AVR XMEGA A Manual • XMEGA A Application Notes This device data sheet only contains part specific ...
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AVR CPU 6.1 Features • 8/16-bit high performance AVR RISC Architecture – 138 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in RAM • Stack Pointer accessible in I/O memory space • Direct ...
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The program memory is In- System Re-programmable Flash memory. 6.3 Register File The fast-access Register File contains 32 x 8-bit general purpose working registers with single clock cycle access time. ...
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Memories 7.1 Features • Flash Program Memory – One linear address space – In-System Programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section ...
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In-System Programmable Flash Program Memory The XMEGA A4 devices contain On-chip In-System Programmable Flash memory for program storage, see Flash address location is 16 bits. The Program Flash memory space is divided into Application and Boot sections. Both sections ...
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... Module Address Map” on page 7.4.2 SRAM Data Memory The XMEGA A4 devices have internal SRAM memory for data storage. 8069Q–AVR–12/10 Figure 7-2 on page 12. To simplify development, the memory map for all Byte Address ATxmega32A4 0 I/O Registers (4 KB) FFF 1000 EEPROM (1 KB) ...
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... Chip Erase commands that erase the Flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase session and on-chip debug sessions. 8069Q–AVR–12/10 Table 7-1 on page Device ID bytes for XMEGA A4 devices. Device Byte 2 ATxmega16A4 ATxmega32A4 ATxmega64A4 ATxmega128A4 XMEGA A4 13. The serial number consist of Device ID bytes Byte 1 41 ...
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... The most significant bits in the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page. Table 7-3. Devices EEPROM Size ATxmega16A4 1 KB ATxmega32A4 1 KB ATxmega64A4 2 KB ATxmega128A4 2 KB 8069Q–AVR–12/10 shows the Flash Program Memory organization. Flash write and erase Number of words and Pages in the Flash ...
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DMAC - Direct Memory Access Controller 8.1 Features • Allows High-speed data transfer – From memory to peripheral – From memory to memory – From peripheral to memory – From peripheral to peripheral • 4 Channels • From 1 ...
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Event System 9.1 Features • Inter-peripheral communication and signalling with minimum latency • CPU and DMA independent operation • 8 Event Channels allow for signals to be routed at the same time • Events can be ...
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Figure 9-1. The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators (ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Com- munication Module (IRCOM). Events can also be generated from software (CPU). All ...
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System Clock and Clock options 10.1 Features • Fast start-up time • Safe run-time clock switching • Internal Oscillators: – 32 MHz run-time calibrated RC oscillator – 2 MHz run-time calibrated RC oscillator – 32.768 kHz calibrated RC oscillator ...
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Figure 10-1. Clock system overview Run-Time Calibrated Each clock source is briefly described in the following sub-sections. 10.3 Clock Options 10.3.1 32 kHz Ultra Low Power Internal Oscillator The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very ...
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Crystal Oscillator The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be used as system clock source or as asynchronous clock source for the Real Time Counter. 10.3.4 0.4 ...
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Power Management and Sleep Modes 11.1 Features • 5 sleep modes – Idle – Power-down – Power-save – Standby – Extended standby • Power Reduction registers to disable clocks to unused peripherals 11.2 Overview The XMEGA A4 provides various ...
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Extended Standby Mode Extended Standby mode is identical to Power-save mode with the exception that all enabled system clock sources are kept running while the CPU and Peripheral clocks are stopped. This reduces the wake-up time when external crystals ...
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System Control and Reset 12.1 Features • Multiple reset sources for safe operation and device reset – Power-On Reset – External Reset – Watchdog Reset – Brown-Out Reset – PDI reset – Software reset • Asynchronous reset – No ...
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PDI reset The MCU can be reset through the Program and Debug Interface (PDI). 12.3.6 Software reset The MCU can be reset by the CPU writing to a special I/O register through a timed sequence. 13. WDT - Watchdog ...
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PMIC - Programmable Multi-level Interrupt Controller 14.1 Features • Separate interrupt vector for each interrupt • Short, predictable interrupt response time • Programmable Multi-level Interrupt Controller – 3 programmable interrupt levels – Selectable priority scheme within low level interrupts ...
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Table 14-1. Reset and Interrupt Vectors (Continued) Program Address (Base Address) Source 0x040 NVM_INT_base 0x044 PORTB_INT_base 0x056 PORTE_INT_base 0x05A TWIE_INT_base 0x05E TCE0_INT_base 0x06A TCE1_INT_base 0x074 USARTE0_INT_base 0x080 PORTD_INT_base 0x084 PORTA_INT_base 0x088 ACA_INT_base 0x08E ADCA_INT_base 0x09A TCD0_INT_base 0x0A6 TCD1_INT_base 0x0AE SPID_INT_vector ...
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I/O Ports 15.1 Features • Selectable input and output configuration for each pin individually • Flexible pin configuration through dedicated Pin Configuration Register • Synchronous and/or asynchronous input sensing with port interrupts and events – Sense both edges – ...
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Push-pull Figure 15-1. I/O configuration - Totem-pole 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input) 15.3.3 Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input) 15.3.4 Bus-keeper The bus-keeper’s weak output produces the ...
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Figure 15-4. I/O configuration - Totem-pole with bus-keeper 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down Figure 15-6. I/O configuration - Wired-AND with optional pull-up 8069Q–AVR–12/10 DIRn OUTn INn OUTn INn INn OUTn XMEGA ...
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Input sensing • Sense both edges • Sense rising edges • Sense falling edges • Sense low level Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure ...
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T/C - 16-bit Timer/Counter 16.1 Features • Five 16-bit Timer/Counters – Three Timer/Counters of type 0 – Two Timer/Counters of type 1 • Three Compare or Capture (CC) Channels in Timer/Counter 0 • Two Compare or Capture (CC) Channels ...
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Figure 16-1. Overview of a Timer/Counter and closely related peripherals Timer/Counter Base Counter Timer Period Compare/Capture Channel B Compare/Capture Channel A Comparator The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by 2 bits (4x). This is ...
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AWEX - Advanced Waveform Extension 17.1 Features • Output with complementary output from each Capture channel • Four Dead Time Insertion (DTI) Units, one for each Capture channel • 8-bit DTI Resolution • Separate High and Low Side Dead-Time ...
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Hi-Res - High Resolution Extension 18.1 Features • Increases Waveform Generator resolution by 2-bits (4x) • Supports Frequency, single- and dual-slope PWM operation • Supports the AWEX when this is enabled and used for the same Timer/Counter 18.2 Overview ...
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RTC - 16-bit Real-Time Counter 19.1 Features • 16-bit Timer • Flexible Tick resolution ranging from 32.768 kHz • One Compare register • One Period register • Clear timer on Overflow or Compare Match • Overflow ...
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TWI - Two-Wire Interface 20.1 Features • Two Identical TWI peripherals • Simple yet Powerful and Flexible Communication Interface • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space Allows ...
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SPI - Serial Peripheral Interface 21.1 Features • Two Identical SPI peripherals • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of ...
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USART 22.1 Features • Five Identical USART peripherals • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High-resolution Arithmetic Baud Rate Generator • Supports Serial ...
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IRCOM - IR Communication Module 23.1 Features • Pulse modulation/demodulation for infrared communication • Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps • Selectable pulse modulation scheme – 3/16 of baud rate period – Fixed ...
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Crypto Engine 24.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) Crypto module • DES Instruction – Encryption and Decryption – Single-cycle DES instruction – Encryption/Decryption in 16 clock cycles per 8-byte block • ...
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ADC - 12-bit Analog to Digital Converter 25.1 Features • One ADC with 12-bit resolution • 2 Msps sample rate • Signed and Unsigned conversions • 4 result registers with individual input channel control • 12 single ended inputs ...
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Figure 25-1. ADC overview Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be sampled within 1.5 µs without any intervention by the application other than starting the conversion. The results ...
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DAC - 12-bit Digital to Analog Converter 26.1 Features • One DAC with 12-bit resolution • Msps conversion rate • Flexible conversion range • Multiple trigger sources • 1 continuous output or 2 Sample and Hold ...
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AC - Analog Comparator 27.1 Features • Two Analog Comparators • Selectable Power vs. Speed • Selectable hysteresis – mV • Analog Comparator output available on pin • Flexible Input Selection – All pins on ...
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Figure 27-1. Analog comparator overview Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled 8069Q–AVR–12/10 XMEGA A4 + Pin 0 output AC0 - Interrupt sensitivity control + AC1 - ...
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Input Selection The Analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. One pair of analog comparators is shown in Figure 27-1 on page ...
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OCD - On-chip Debug 28.1 Features • Complete Program Flow Control – Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor • Debugging on C and high-level language source code level • Debugging on Assembler and disassembler level ...
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Program and Debug Interfaces 29.1 Features • PDI - Program and Debug Interface (Atmel proprietary 2-pin interface) • Access to the OCD system • Programming of Flash, EEPROM, Fuses and Lock Bits 29.2 Overview The programming and debug facilities ...
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Pinout and Pin Functions The pinout of XMEGA A4 is shown in I/O functionality, each pin may have several functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate ...
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Communication functions SCL SDA XCKn RXDn TXDn SS MOSI MISO SCK 30.1.6 Oscillators, Clock and Event TOSCn XTALn 30.1.7 Debug/System functions RESET PDI_CLK PDI_DATA 8069Q–AVR–12/10 Serial Clock for TWI Serial Data for TWI Transfer Clock for USART n Receiver ...
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Alternate Pin Functions The tables below shows the main and alternate pin functions for all pins on each port. It also shows which peripheral which make use of or enable the alternate pin function. Table 30-1. Port A - ...
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Table 30-4. Port D - Alternate functions PORTD PIN # INTERRUPT GND 18 VCC 19 PD0 20 SYNC PD1 21 SYNC PD2 22 SYNC/ASYNC PD3 23 SYNC PD4 24 SYNC PD5 25 SYNC PD6 26 SYNC PD7 27 SYNC Table ...
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Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA A4. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual. Base Address 0x0000 0x0010 ...
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Instruction Set Summary Mnemonics Operands Description ADD Rd, Rr Add without Carry ADC Rd, Rr Add with Carry ADIW Rd, K Add Immediate to Word SUB Rd, Rr Subtract without Carry SUBI Rd, K Subtract Immediate SBC Rd, Rr ...
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Mnemonics Operands Description CALL k call Subroutine RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register ...
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Mnemonics Operands Description LD Rd, -Y Load Indirect and Pre-Decrement LDD Rd, Y+q Load Indirect with Displacement LD Rd, Z Load Indirect LD Rd, Z+ Load Indirect and Post-Increment LD Rd, -Z Load Indirect and Pre-Decrement LDD Rd, Z+q Load ...
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Mnemonics Operands Description ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear SBI A, b Set Bit in I/O Register ...
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Packaging information 33.1 44A PIN 1 IDENTIFIER e C 0°~7° Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions ...
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D Marked Pin TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. Package Drawing Contact: packagedrawings@atmel.com 8069Q–AVR–12/10 E Pin #1 Corner Pin #1 Option A 1 ...
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A1 BALL BALL CORNER b Package Drawing Contact: packagedrawings@atmel.com 8069Q–AVR–12/ TOP VIEW 0.35 ± 0.05 ...
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Electrical Characteristics All typical values are measured 25°C unless other temperature condition is given. All min- imum and maximum values are valid across operating temperature and voltage unless other conditions are given. 34.1 Absolute Maximum Ratings* ...
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Table 34-1. Current Consumption (Continued) Symbol Parameter Power-save mode I CC Reset Current Consumption (2) Module current consumption RC32M RC32M w/DFLL RC2M RC2M w/DFLL RC32K PLL Watchdog normal mode BOD Continuous mode BOD Sampled mode Internal 1.00 V ref Temperature ...
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Speed Table 34-2. Symbol Clk The maximum CPU clock frequency of the XMEGA A4 devices is depending Figure 34-1 on page 63 Figure 34-1. Operating Frequency vs.Vcc 8069Q–AVR–12/10 Operating voltage and frequency Parameter ...
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Flash and EEPROM Memory Characteristics Table 34-3. Endurance and Data Retention Symbol Parameter Flash EEPROM Table 34-4. Programming time Symbol Parameter Chip Erase Flash EEPROM Notes: 1. Programming is timed from the internal 2 MHz oscillator. 2. EEPROM is ...
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ADC Characteristics Table 34-5. ADC Characteristics Symbol Parameter RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Gain Error Offset Error ADC ADC Clock frequency clk Conversion rate Conversion time (propagation delay) Sampling Time Conversion range AVCC Analog Supply Voltage ...
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DAC Characteristics Table 34-7. DAC Characteristics Symbol Parameter INL Integral Non-Linearity DNL Differential Non-Linearity F Conversion rate clk AREF External reference voltage Reference input impedance Max output voltage Min output voltage Offset factory calibration accuracy Gain factory calibration accuracy ...
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Brownout Detection Characteristics Table 34-10. Brownout Detection Characteristics Symbol Parameter BOD level 0 falling Vcc BOD level 1 falling Vcc BOD level 2 falling Vcc BOD level 3 falling Vcc BOD level 4 falling Vcc BOD level 5 falling ...
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POR Characteristics Table 34-12. Power-on Reset Characteristics Symbol Parameter V POR threshold voltage falling V POT- V POR threshold voltage rising V POT+ 34.12 Reset Characteristics Table 34-13. Reset Characteristics Symbol Parameter Minimum reset pulse width Reset threshold voltage ...
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Table 34-18. External 32.768kHz Crystal Oscillator and TOSC characteristics Symbol Parameter SF Safety factor Recommended crystal equivalent ESR/R 1 series resistance (ESR) Input capacitance between TOSC C IN_TOSC pins Note: 1. See Figure 34-2 on page 69 Figure 34-2. TOSC ...
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Typical Characteristics 35.1 Active Supply Current Figure 35-1. Active Supply Current vs. Frequency Figure 35-2. Active Supply Current vs. Frequency 8069Q–AVR–12/ 1.0 MHz External clock 25°C. SYS 700 600 500 400 300 200 ...
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Figure 35-3. Active Supply Current vs. Vcc Figure 35-4. Active Supply Current vs. VCC 8069Q–AVR–12/ 1.0 MHz External Clock. SYS 800 700 600 500 400 300 200 100 0 1.6 1.8 2 2.2 2 32.768 kHz ...
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Figure 35-5. Active Supply Current vs. Vcc Figure 35-6. Active Supply Current vs. Vcc 8069Q–AVR–12/ 2.0 MHz internal RC. SYS 1600 1400 1200 1000 800 600 400 200 0 1.6 1.8 2 2.2 2 MHz ...
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Figure 35-7. Active Supply Current vs. Vcc 35.2 Idle Supply Current Figure 35-8. Idle Supply Current vs. Frequency 8069Q–AVR–12/ MHz internal RC. SYS 2.7 2.8 2.9 3 3.1 ...
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Figure 35-9. Idle Supply Current vs. Frequency Figure 35-10. Idle Supply Current vs. Vcc 8069Q–AVR–12/ MHz 25°C. SYS 1 Frequency [MHz] ...
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Figure 35-11. Idle Supply Current vs. Vcc Figure 35-12. Idle Supply Current vs. Vcc 8069Q–AVR–12/ 32.768 kHz internal RC. SYS 1.6 1.8 2 2.2 2 2.0 MHz ...
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Figure 35-13. Idle Supply Current vs. Vcc Figure 35-14. Idle Supply Current vs. Vcc 8069Q–AVR–12/ MHz internal RC prescaled to 8 MHz. SYS 3000 2500 2000 1500 1000 500 0 1.6 1.8 2 2.2 2 ...
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Power-down Supply Current Figure 35-15. Power-down Supply Current vs. Temperature Figure 35-16. Power-down Supply Current vs. Temperature 8069Q–AVR–12/10 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -40 -30 -20 - Temperature [°C] With WDT and ...
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Power-save Supply Current Figure 35-17. Power-save Supply Current vs. Temperature 35.5 Pin Pull-up Figure 35-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage 8069Q–AVR–12/10 With WDT, sampled BOD and RTC from ULP enabled. 3 2.5 2 1.5 1 0.5 ...
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Figure 35-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage Figure 35-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage 8069Q–AVR–12/ 3.0V. CC 160 140 120 100 0 3.3V. ...
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Pin Output Voltage vs. Sink/Source Current Figure 35-21. I/O Pin Output Voltage vs. Source Current Figure 35-22. I/O Pin Output Voltage vs. Source Current 8069Q–AVR–12/10 Vcc = 1.8V. 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 ...
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Figure 35-23. I/O Pin Output Voltage vs. Source Current Figure 35-24. I/O Pin Output Voltage vs. Sink Current 8069Q–AVR–12/10 Vcc = 3.3V. 3.5 3 2.5 2 1.5 1 0.5 0 -20 -18 -16 -14 -12 Vcc = 1.8V. 1.8 1.6 ...
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Figure 35-25. I/O Pin Output Voltage vs. Sink Current Figure 35-26. I/O Pin Output Voltage vs. Sink Current 8069Q–AVR–12/10 Vcc = 3.0V. 0.7 0.6 0.5 0.4 0.3 0.2 0 Vcc = 3.3V. 0.7 0.6 ...
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Pin Thresholds and Hysteresis Figure 35-27. I/O Pin Input Threshold Voltage vs. V Figure 35-28. I/O Pin Input Threshold Voltage vs. V 8069Q–AVR–12/ I/O Pin Read as “1”. IH 2.5 2 1.5 1 0.5 0 1.6 1.8 ...
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Figure 35-29. I/O Pin Input Hysteresis vs. V Figure 35-30. Reset Input Threshold Voltage vs. V 8069Q–AVR–12/10 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2 2.2 2 I/O Pin Read as “1”. IH 1.8 1.6 ...
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Figure 35-31. Reset Input Threshold Voltage vs. V 35.8 Bod Thresholds Figure 35-32. BOD Thresholds vs. Temperature 8069Q–AVR–12/ I/O Pin Read as “0”. IL 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 ...
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Figure 35-33. BOD Thresholds vs. Temperature 35.9 Analog Comparator Figure 35-34. Analog Comparator Hysteresis vs. V 8069Q–AVR–12/10 BOD Level = 2.9V. 3.03 3.02 3.01 Rising Vcc 3 2.99 2.98 2.97 2.96 Falling Vcc 2.95 2.94 2.93 -40 -30 -20 -10 ...
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Figure 35-35. Analog Comparator Hysteresis vs. V Figure 35-36. Analog Comparator Propagation Delay vs. V 8069Q–AVR–12/10 High-speed, Large hysteresis 1.6 1.8 2 2.2 2.4 High-speed. 180 162 144 126 108 ...
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Oscillators and Wake-up Time 35.10.1 Internal 32.768 kHz Oscillator Figure 35-37. Internal 32.768 kHz Oscillator Calibration Step Size 35.10.2 Internal 2 MHz Oscillator Figure 35-38. Internal 2 MHz Oscillator CALA Calibration Step Size -0.10 % -0.20 % -0.30 % ...
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Figure 35-39. Internal 2 MHz Oscillator CALB Calibration Step Size 35.10.3 Internal 32 MHZ Oscillator Figure 35-40. Internal 32 MHz Oscillator CALA Calibration Step Size 8069Q–AVR–12/10 ° - 3V. CC 3.00 % 2.50 ...
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Figure 35-41. Internal 32 MHz Oscillator CALB Calibration Step Size 35.11 Module current consumption Figure 35-42. AC current consumption vs. Vcc 8069Q–AVR–12/10 ° - 3V. CC 3.00 % 2.50 % 2.00 % 1.50 ...
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Figure 35-43. Power-up current consumption vs. Vcc 35.12 Reset Pulsewidth Figure 35-44. Minimum Reset Pulse Width vs. Vcc 8069Q–AVR–12/10 600 500 400 300 200 100 0 0.4 0.6 0.8 1 100 1.6 1.8 2 2.2 ...
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PDI Speed Figure 35-45. PDI Speed vs. Vcc 8069Q–AVR–12/ 1.6 1.8 2 2.2 2.4 XMEGA A4 2.6 2.8 3 3.2 3 °C 3.6 92 ...
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... Errata 36.1 ATxmega16A4, ATxmega32A4 36.1.1 rev. A/B • Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously • VCC voltage scaler for AC is non-linear • ADC has increased INL error for some operating conditions • ADC gain stage output range is limited to 2.4 V • ...
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Figure 36-1. Analog Comparator Voltage Scaler vs. Scalefac Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition ...
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Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2 order to get a cor- rect result, or keep ADC voltage reference below 2 ADC Event on compare match non-functional ADC signalling ...
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Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 11. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when ...
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For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. 17. NMI Flag for ...
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Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared ...
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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revisions in this section are referring to the document revision. 37.1 8069Q – 12/ ...
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37.5 8069M – 02/ 37.6 8069L – 11/ 37.7 8069K – 06/ 37.8 8069J – 04/ 37.9 8069I – 03/ 8069Q–AVR–12/10 ...
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37.10 8069H – 11/ 37.11 8069G – 10/ 37.12 8069F – 09/ 37.13 8069E – 08/ 37.14 8069D – 08/ 8069Q–AVR–12/10 ...
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Updated Figure 2-1 on page 3 ...
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Table of Contents Features ..................................................................................................... 1 Typical Applications ................................................................................ 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 3 3 Overview ................................................................................................... 5 4 Resources ................................................................................................. 7 5 Disclaimer ................................................................................................. 7 6 AVR CPU ................................................................................................... 8 7 Memories ................................................................................................ ...
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Power Management and Sleep Modes ................................................. 21 12 System Control and Reset .................................................................... 23 13 WDT - Watchdog Timer ......................................................................... 24 14 PMIC - Programmable Multi-level Interrupt Controller ....................... 25 15 I/O Ports .................................................................................................. 27 16 T/C - 16-bit ...
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RTC - 16-bit Real-Time Counter ............................................................ 35 20 TWI - Two-Wire Interface ....................................................................... 36 21 SPI - Serial Peripheral Interface ............................................................ 37 22 USART ..................................................................................................... 38 23 IRCOM - IR Communication Module .................................................... 39 24 Crypto Engine ........................................................................................ 40 ...
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Pinout and Pin Functions ...................................................................... 49 31 Peripheral Module Address Map .......................................................... 53 32 Instruction Set Summary ...................................................................... 54 33 Packaging information .......................................................................... 58 34 Electrical Characteristics ...................................................................... 61 35 Typical Characteristics .......................................................................... 70 XMEGA A4 iv 29.1Features ................................................................................................................48 ...
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... Thresholds .....................................................................................................85 35.9Analog Comparator ...............................................................................................86 35.10Oscillators and Wake-up Time ............................................................................88 35.11Module current consumption ...............................................................................90 35.12Reset Pulsewidth .................................................................................................91 35.13PDI Speed ...........................................................................................................92 36 Errata ....................................................................................................... 93 36.1ATxmega16A4, ATxmega32A4 .............................................................................93 37 Datasheet Revision History .................................................................. 99 37.18069Q – 12/10 .......................................................................................................99 37.28069P – 09/10 .......................................................................................................99 37.38069O – 08/10 .......................................................................................................99 37.48069N – 02/10 .......................................................................................................99 37.58069M – 02/10 ....................................................................................................100 37.68069L – 11/09 .....................................................................................................100 37.78069K – 06/09 .....................................................................................................100 37.88069J – 04/09 ......................................................................................................100 37.98069I – ...
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