SAM3N4B Atmel Corporation, SAM3N4B Datasheet - Page 106

• Manufacturer Part Number: SAM3N4B
• Manufacturer: Atmel Corporation

Specifications of SAM3N4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.13.1.4
10.13.1.5
106
ADD
SUBS
RSB
ADCHI
SAM3N
Condition flags
Examples
R2, R1, R3
R8, R6, #240
R4, R4, #1280
R11, R0, R3
When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
If S is specified, these instructions update the N, Z, C and V flags according to the result.
• Rd can be SP only in ADD and SUB, and only with the additional restrictions:
• Rn can be SP only in ADD and SUB
• Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:
• with the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and
• bit[0] of the value written to the PC is ignored
• a branch occurs to the address created by forcing bit[0] of that value to 0.
SUB, and only with the additional restrictions:
– Rn must also be SP
– any shift in Operand2 must be limited to a maximum of 3 bits using LSL
– you must not specify the S suffix
– Rm must not be PC and must not be SP
– if the instruction is conditional, it must be the last instruction in the IT block
– you must not specify the S suffix
– the second operand must be a constant in the range 0 to 4095.
–
– When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded
– If you want to generate the address of an instruction, you have to adjust the constant
to b00 before performing the calculation, making the base address for the calculation
word-aligned.
based on the value of the PC. ARM recommends that you use the ADR instruction
instead of ADD or SUB with Rn equal to the PC, because your assembler
automatically calculates the correct constant for the ADR instruction.
; Sets the flags on the result
; Subtracts contents of R4 from 1280
; Only executed if C flag set and Z
; flag clear
11011A–ATARM–04-Oct-10