SAM3S4C Atmel Corporation, SAM3S4C Datasheet - Page 40

• Manufacturer Part Number: SAM3S4C
• Manufacturer: Atmel Corporation

Specifications of SAM3S4C

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 39
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 48
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.10 Real Time Clock
10.11 General Purpose Backup Registers
10.12 Nested Vectored Interrupt Controller
10.13 Chip Identification
40
SAM3S Summary
Table 10-1.
• Low power consumption
• Full asynchronous design
• Two hundred year calendar
• Programmable Periodic Interrupt
• Alarm and update parallel load
• Control of alarm and update Time/Calendar Data In
• Eight 32-bit general-purpose backup registers
• Thirty maskable external interrupts
• Sixteen priority levels
• Processor state automatically saved on interrupt entry, and restored on
• Dynamic reprioritization of interrupts
• Priority grouping.
• Support for tail-chaining and late arrival of interrupts.
• Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no
• Chip Identifier (CHIPID) registers permit recognition of the device and its revision.
• JTAG ID: 0x05B2D03F
instruction overhead.
ATSAM3S4C (Rev A)
ATSAM3S2C (Rev A)
ATSAM3S1C (Rev A)
ATSAM3S4A (Rev A)
ATSAM3S2A (Rev A)
ATSAM3S1A (Rev A)
ATSAM3S4B (Rev A)
ATSAM3S2B (Rev A)
ATSAM3S1B (Rev A)
– Alarm register capable to generate a wake-up of the system through the Shut Down
– selection of preempting interrupt levels and non-preempting interrupt levels.
– back-to-back interrupt processing without the overhead of state saving and
Controller
restoration between interrupts.
Chip Name
SAM3S Chip IDs Register
Flash Size
(KBytes)
256
128
256
128
256
128
64
64
64
Pin Count
100
100
100
48
48
48
64
64
64
DBGU_CIDR
0x28AA0760
0x28A90560
0x28800960
0x288A0760
0x28890560
0x28900960
0x289A0760
0x28990560
0x28A00960
6500CS–ATARM–24-Jan-11
CHIPID_EXID
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0