SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 247

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Level one
Level two descriptor 3-14
Line length encoding 2-11
L4 bit 2-13
M
M bit 2-10, 2-14
MCR, accessing CP15 2-4
MCR/MRC instructions 8-6
Memory coherency 6-9
Memory management unit (MMU) 3-2
Memory Region Remap Register B-15
Miscellaneous signals A-10
MMU
MMU test operations B-5
Modified virtual address 2-4
MRC, accessing CP15 2-4
Multi-AHB system 6-8
Multiple banks of RAM 5-21
Multiplier bit 2-10
MVA 2-4
ARM DDI0198D
descriptor 3-8
descriptor, accessing 3-8
fetch 3-8
accessible registers 3-4
accessing main TLB entries B-6
accessing MVA tag B-5, B-7
accessing PA and access permissions
accessing tag in lockdown TLB entry
debug control register B-13
disabling 3-30
enable/disable 2-14
enabling 3-29
fault checking 3-26
faults 3-21
protection 2-14
RAMs 12-3
test register B-5
transferring lockdown TLB entry to
transferring main TLB entry to RAM
B-6
B-6
RAM B-6
B-6
Copyright © 2001-2003 ARM Limited. All rights reserved.
N
nCPINSTRVALID 8-13
Noncachable code 7-2
Noncachable instruction fetches 7-2
Numerical conventions xx
O
Optimizing
P
PA 2-4
Page tables 3-7
Permission fault 3-28
Physical address 2-4
Power management 12-2
Prefetch ICache line 2-21
Privileged instructions 8-9
Process ID register 2-33
Process identifier 2-34
Product revision status xvi
R
R bit, ROM protection 2-14
Register descriptions 2-7
Registers
for power 5-22
for speed 5-23
dynamic 12-2
static 12-3
cache debug control B-12
cache lockdown 2-26
cache operations 2-21
cache type 2-7, 2-8
context ID 2-35
control 2-12
CP15 2-3
debug override B-2
debug/test address B-4
domain access control 2-17
fault address 2-20
fault status 2-18
FCSE PID 2-34
Registers (continued)
Revision status xvi
RR bit 2-13
S
S bit 2-9, 2-14
SBO 2-5
SBZ 2-5
SBZP 2-5
Scan chain 15 11-2
Section
Self-modifying code 7-2
Set way format 4-9
Should Be One 2-5
Should Be Zero 2-5
Should Be Zero or Preserved 2-5
Signal descriptions A-2
Signal naming conventions xix
Signal properties and requirements A-2
Signals
Single-layer AHB 6-7
Size bit encoding 2-30
Size field 2-9, 2-30
Small page references, translating 3-18
ID code 2-7, 2-8
Memory Region Remap B-15
MMU debug control B-13
MMU test B-5
process ID 2-33
system control 2-3
TCM region 2-26
TCM status 2-7, 2-12
test B-2
test and debug 2-36
TLB lockdown 2-32
TLB operations 2-24
trace control B-5
translation table base 2-17, 3-6
descriptor 3-10
references, translating 3-13
AHB A-3
coprocessor interface A-5
debug A-7
ETM interface A-12
JTAG A-9
miscellaneous A-10
TCM interface A-14
Index-3
Index