SAM9G46 Atmel Corporation, SAM9G46 Datasheet - Page 121
SAM9G46
Manufacturer Part Number
SAM9G46
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G46.pdf
(58 pages)
Specifications of SAM9G46
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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5.3.3
ARM DDI0198D
Multi-cycle access timing
If non zero wait state memory is used for TCM, then the DRWAIT/IRWAIT signals
are used to wait the ARM926EJ-S. The wait information for a data cycle is pipelined so
that the value of DRWAIT/IRWAIT pertains to the following data cycle, which
corresponds to the request cycle for the first data cycle. If there is no active TCM access
then the value on DRWAIT/IRWAIT is ignored. This allows the wait signals to be
generated speculatively.
Figure 5-6 shows how the speculative generation of IRWAIT can be used to generate a
single wait state for every ITCM access.
In cycle T1, IRWAIT is asserted but no request is made.
In cycle T2, IRWAIT is asserted and a request is made.
In cycle T3, IRWAIT is deasserted indicating that the access to A will complete in the
following cycle.
In cycle T4, IRWAIT is asserted and a request is made. The access to A completes.
In cycle T5, IRWAIT is deasserted indicating that the access to B will complete in the
following cycle.
In cycle T6, IRWAIT is asserted. No request is made. The access to B completes.
The logic required for the above example corresponds to the two-state state machine
shown in Figure 5-7 on page 5-14.
Copyright © 2001-2003 ARM Limited. All rights reserved.
IRADDR
IRWAIT
Figure 5-6 Generating a single wait state for ITCM accesses using IRWAIT
IRCS
IRRD
CLK
T1
T2
A
T3
T4
Tightly-Coupled Memory Interface
B
I(A)
T5
T6
I(B)
5-13
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