LT1720IS8 Linear Technology, LT1720IS8 Datasheet - Page 9

• Manufacturer Part Number: LT1720IS8
• Description: IC COMP R-RINOUT DUAL 8-SOIC
• Manufacturer: Linear Technology
• Series: UltraFast™r
• Type: General Purposer

Specifications of LT1720IS8

• Number Of Elements: 2
• Output Type: CMOS, Rail-to-Rail, TTL
• Voltage - Supply: 2.7 V ~ 6 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

High Speed Design Considerations
Application of high speed comparators is often plagued
by oscillations. The LT1720/LT1721 have 4mV of internal
hysteresis, which will prevent oscillations as long as
parasitic output to input feedback is kept below 4mV.
However, with the 2V/ns slew rate of the LT1720/LT1721
outputs, a 4mV step can be created at a 100Ω input source
with only 0.02pF of output to input coupling. The pinouts
of the LT1720/LT1721 have been arranged to minimize
problems by placing the most sensitive inputs (invert-
ing) away from the outputs, shielded by the power rails.
The input and output traces of the circuit board should
also be separated, and the requisite level of isolation is
readily achieved if a topside ground plane runs between
the outputs and the inputs. For multilayer boards where
the ground plane is internal, a topside ground or supply
trace should be run between the inputs and outputs, as
illustrated in Figure 1.
APPLICATIONS INFORMATION
Figure 1a shows a typical topside layout of the LT1720
on such a multilayer board. Shown is the topside metal
etch including traces, pin escape vias, and the land pads
for an SO-8 LT1720 and its adjacent X7R 10nF bypass
capacitor in a 1206 case.
The ground trace from Pin 5 runs under the device up to
the bypass capacitor, shielding the inputs from the out-
puts. Note the use of a common via for the LT1720 and
the bypass capacitor, which minimizes interference from
high frequency energy running around the ground plane
or power distribution traces.
Figure 1b shows a typical topside layout of the LT1721
on a multilayer board. In this case, the power and ground
traces have been extended to the bottom of the device
solely to act as high frequency shields between input and
output traces.
Figure 1. Typical Topside Metal for Multilayer PCB Layouts
(a)
(b)
17201 F01
Although both V
the LT1721, they must be shorted together externally as
well in order for both to function as shields. The same is
true for the two GND pins.
The supply bypass should include an adjacent 10nF ce-
ramic capacitor and a 2.2μF tantalum capacitor no farther
than 5cm away; use more capacitance if driving more
than 4mA loads. To prevent oscillations, it is helpful to
balance the impedance at the inverting and noninverting
inputs; source impedances should be kept low, preferably
1kΩ or less.
The outputs of the LT1720/LT1721 are capable of very
high slew rates. To prevent overshoot, ringing and other
problems with transmission line effects, keep the output
traces shorter than 10cm, or be sure to terminate the lines
to maintain signal integrity. The LT1720/LT1721 can drive
DC terminations of 250Ω or more, but lower characteristic
impedance traces can be driven with series termination
or AC termination topologies.
Hysteresis
The LT1720/LT1721 include internal hysteresis, which
makes them easier to use than many other comparable
speed comparators.
The input-output transfer characteristic is illustrated in
Figure 2 showing the defi nitions of V
upon the two measurable trip points. The hysteresis band
makes the LT1720/LT1721 well behaved, even with slowly
moving inputs.
V
OL
Figure 2. Hysteresis I/O Characteristics
V
TRIP
V
OS
–
CC
=
0
V
(= V
TRIP
pins are electrically shorted internal to
TRIP
+
+ V
2
V
HYST
+
TRIP
– V
TRIP
–
V
LT1720/LT1721
HYST
–
)
/2
V
TRIP
+
OS
and V
V
IN
V
OH
= V
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IN
HYST
+
– V
IN
–
based
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