LT1016IS8#TR Linear Technology, LT1016IS8#TR Datasheet - Page 12

IC COMPARATOR 10NS HI SPD 8SOIC

LT1016IS8#TR

Manufacturer Part Number
LT1016IS8#TR
Description
IC COMPARATOR 10NS HI SPD 8SOIC
Manufacturer
Linear Technology
Series
UltraFast™r
Type
General Purposer
Datasheet

Specifications of LT1016IS8#TR

Number Of Elements
1
Output Type
CMOS, Complementary, TTL
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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LT1016
APPLICATIO S I FOR ATIO
Another output-caused fault is shown in Figure 13. The
output transitions are initially correct but end in a ringing
condition. The key to the solution here is the ringing. What
is happening is caused by an output lead that is too long.
The output lead looks like an unterminated transmission
line at high frequencies and reflections occur. This ac-
counts for the abrupt reversal of direction on the leading
edge and the ringing. If the comparator is driving TTL this
may be acceptable, but other loads may not tolerate it. In
this instance, the direction reversal on the leading edge
might cause trouble in a fast TTL load. Keep output lead
lengths short. If they get much longer than a few inches,
terminate with a resistor (typically 250 W to 400 W ).
12
INPUT
±3V
1V/DIV
Figure 13. Lengthy, Unterminated Output Lines
Ring from Reflections
220Ω
5V
Q5
2N2222
LT1009
2.5V
U
5.1k
0.1µF
U
1N4148
1.5k
50ns/DIV
1.5k
5.1k
Q2
2N2907A
820Ω
390Ω
W
1.5k
470Ω
Figure 14. 200ns Sample-and-Hold
–15V
1016 F13
U
Q1
2N5160
Q3
2N2369
Q4
2N2907A
1N4148
100Ω
100Ω
390Ω
1000pF
(POLYSTYRENE)
8pF
– 5V
1k
200ns-0.01% Sample-and-Hold Circuit
Figure 14’s circuit uses the LT1016’s high speed to
improve upon a standard circuit function. The 200ns
acquisition time is well beyond monolithic sample-and-
hold capabilities. Other specifications exceed the best
commercial unit’s performance. This circuit also gets
around many of the problems associated with standard
sample-and-hold approaches, including FET switch errors
and amplifier settling time. To achieve this, the LT1016’s
high speed is used in a circuit which completely abandons
traditional sample-and-hold methods.
Important specifications for this circuit include:
When the sample-and-hold line goes low, a linear ramp
starts just below the input level and ramps upward. When
the ramp voltage reaches the input voltage, A1 shuts off
the ramp, latches itself off and sends out a signal indicat-
ing sampling is complete.
100Ω
1N4148
1k
DELAY
COMP
Q6
2N2222
Acquisition Time
Common Mode Input Range
Droop
Hold Step
Hold Settling Time
Feedthrough Rejection
Q7
2N5486
300Ω
OUTPUT
+
LT1016
LATCH
A1
SN7402
COMMAND (TTL)
SAMPLE-HOLD
SN7402
>>100dB
SN7402
<200ns
1mV/ms
15ns
2mV
±3V
1016 F14
NOW

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