STM8S105C4

Manufacturer Part NumberSTM8S105C4
DescriptionAccess line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash, integrated EEPROM
ManufacturerSTMicroelectronics
STM8S105C4 datasheet
 


Specifications of STM8S105C4

RamUp to 2 KbytesAdvanced Control Timer16-bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization
Two Watchdog TimersWindow watchdog and independent watchdog  
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Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash,
integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C
LQFP48 7x7
LQFP44 10x10
VFQFPN32 5x5
UFQFPN32 5x5
Features
Core
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
Extended instruction set
Memories
Medium-density Flash/EEPROM:
-
Program memory up to 32 Kbytes; data
retention 20 years at 55°C after 10 kcycles
-
Data memory up to 1 Kbytes true data
EEPROM; endurance 300 kcycles
RAM: Up to 2 Kbytes
Clock, reset and supply management
2.95 V to 5.5 V operating voltage
Flexible clock control, 4 master clock sources:
-
Low power crystal resonator oscillator
-
External clock input
-
Internal, user-trimmable 16 MHz RC
-
Internal low power 128 kHz RC
Clock security system with clock monitor
Power management:
-
Low power modes (wait, active-halt, halt)
-
Switch-off peripheral clocks individually
Permanently active, low consumption power-on
and power-down reset
September 2010
Interrupt management
Nested interrupt controller with 32 interrupts
Up to 37 external interrupts on 6 vectors
Timers
LQFP32 7x7
2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM)
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
SDIP32 400 ml
insertion and flexible synchronization
8-bit basic timer with 8-bit prescaler
Auto wake-up timer
Window and independent watchdog timers
Communications interfaces
UART with clock output for synchronous
operation, Smartcard, IrDA, LIN
SPI interface up to 8 Mbit/s
2
I
C interface up to 400 Kbit/s
Analog-to-digital converter (ADC)
10-bit, ±1 LSB ADC with up to 10 multiplexed
channels, scan mode and analog watchdog
I/Os
Up to 38 I/Os on a 48-pin package including 16
high sink outputs
Highly robust I/O design, immune against current
injection
Development support
Embedded single wire interface module (SWIM)
for fast on-chip programming and non intrusive
debugging
Unique ID
96-bit unique key for each device
Reference
STM8S105xx
DocID14771 Rev 10
STM8S105xx
Table 1: Device summary
Part number
STM8S105K4, STM8S105K6, STM8S105S4, STM8S105S6,
STM8S105C4, STM8S105C6
www.st.com
1/127

STM8S105C4 Summary of contents

  • Page 1

    ... Embedded single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging Unique ID • 96-bit unique key for each device Reference STM8S105xx DocID14771 Rev 10 STM8S105xx Table 1: Device summary Part number STM8S105K4, STM8S105K6, STM8S105S4, STM8S105S6, STM8S105C4, STM8S105C6 www.st.com 1/127 ...

  • Page 2

    Contents Contents 1 Introduction ..............................................................................................................8 2 Description ...............................................................................................................9 3 Block diagram ........................................................................................................11 4 Product overview ...................................................................................................12 4.1 Central processing unit STM8 .....................................................................................12 4.2 Single wire interface module (SWIM) and debug module (DM) ..................................12 4.3 Interrupt controller .......................................................................................................13 4.4 Flash program ...

  • Page 3

    STM8S105xx 10.1.3 Typical curves ....................................................................................56 10.1.4 Typical current consumption ..............................................................56 10.1.5 Loading capacitor ...............................................................................57 10.1.6 Pin input voltage .................................................................................57 10.2 Absolute maximum ratings ........................................................................................57 10.3 Operating conditions ..................................................................................................59 10.3.1 VCAP external capacitor ....................................................................62 10.3.2 Supply current characteristics ............................................................62 10.3.3 External ...

  • Page 4

    List of tables List of tables Table 1. Device summary .........................................................................................................................1 Table 2. STM8S105xx access line features .............................................................................................9 Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................15 Table 4. TIM timer features ...................................................................................................................17 Table 5. Legend/abbreviations for pinout ...

  • Page 5

    STM8S105xx Table 48. EMS data ..............................................................................................................................101 Table 49. EMI data ...............................................................................................................................102 Table 50. ESD absolute maximum ratings ...........................................................................................103 Table 51. Electrical sensitivities ...........................................................................................................103 Table 52. 48-pin low profile quad flat package mechanical data .........................................................104 Table 53. 44-pin low profile quad ...

  • Page 6

    List of figures List of figures Figure 1. STM8S105xx access line block diagram ................................................................................11 Figure 2. Flash memory organisation ....................................................................................................14 Figure 3. LQFP 48-pin pinout .................................................................................................................22 Figure 4. LQFP 44-pin pinout .................................................................................................................23 Figure 5. LQFP/VFQFPN/UFQFPN 32-pin pinout ................................................................................24 Figure 6. ...

  • Page 7

    STM8S105xx Figure 48. 44-pin low profile quad flat package ...................................................................................106 Figure 49. 32-pin low profile quad flat package ( ........................................................................107 Figure 50. 32-lead very thin fine pitch quad flat no-lead package ( ............................................111 Figure 51. 32-lead, ...

  • Page 8

    Introduction 1 Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. • For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference ...

  • Page 9

    ... Ext. Interrupt pins 35 Timer CAPCOM 9 channels Timer 3 complementary outputs A/D Converter 10 channels High sink I/Os 16 Medium density 32K Flash Program memory (bytes) Data EEPROM 1024 (bytes) RAM (bytes) 2K STM8S105C4 STM8S105S6 16K 32K 1024 1024 2K 2K DocID14771 Rev 10 ...

  • Page 10

    ... Description Device STM8S105C6 Peripheral set Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I Window WDG, Independent WDG, ADC 10/127 STM8S105C4 STM8S105S6 DocID14771 Rev 10 STM8S105xx STM8S105S4 STM8S105K6 STM8S105K4 2 C, UART, ...

  • Page 11

    STM8S105xx 3 Block diagram Figure 1: STM8S105xx access line block diagram Reset POR Single wire debug interf. Master/slave autosynchro LIN master SPI emul. 400 Kbit/s 8 Mbit channels 1/2/4 kHz beep Reset block Clock controller Reset Detector ...

  • Page 12

    Product overview 4 Product overview The following section intends to give an overview of the basic features of the device functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing ...

  • Page 13

    STM8S105xx SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module ...

  • Page 14

    Product overview The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the ...

  • Page 15

    STM8S105xx - 16 MHz high-speed internal RC oscillator (HSI) - 128 kHz low-speed internal RC (LSI) • Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can ...

  • Page 16

    Product overview 4.7 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled ...

  • Page 17

    STM8S105xx 4.10 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, ...

  • Page 18

    Product overview Timer Counter Prescaler size (bits) TIM4 8 Any power of 2 from 1 to 128 4.13 Analog-to-digital converter (ADC1) The STM8S105xx products contain a 10-bit successive approximation A/D converter (ADC1) with multiplexed input channels and ...

  • Page 19

    STM8S105xx • LIN master mode • LIN slave mode Asynchronous communication (UART mode) • Full duplex communication - NRZ standard format (mark/space) • Programmable transmit and receive baud rates Mbit/s (f following any standard baud rate regardless ...

  • Page 20

    Product overview 4.14.3 I²C • I²C master features: - Clock generation - Start and stop generation • I²C slave features: - Programmable I2C address detection - Stop bit detection • Generation and detection of 7-bit/10-bit addressing and general call • ...

  • Page 21

    STM8S105xx 5 Pinout and pin description Type Level Output speed Port and control configuration Reset state Table 5: Legend/abbreviations for pinout tables I= Input Output Power supply CM = CMOS Input Output HS = High sink ...

  • Page 22

    Pinout and pin description 5.1 STM8S105 pinouts and pin description [TIM3_CH1] TIM2_CH3/PA3 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate function remapping option (If the same alternate function ...

  • Page 23

    STM8S105xx 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication ...

  • Page 24

    Pinout and pin description 1. (HS) high sink capability alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 24/127 Figure 5: LQFP/VFQFPN/UFQFPN 32-pin ...

  • Page 25

    STM8S105xx ADC_ETR/TIM2_CH2/PD3(HS) 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a ...

  • Page 26

    Pinout and pin description Pin number Pin name LQFP48 LQFP44 LQFP32/ SDIP32 VFQFPN32/ UFQFPN32 PA3/ TIM2 _CH3 [TIM3 _CH1 PA4 PA5 PA6 - - ...

  • Page 27

    STM8S105xx Pin number Pin name LQFP48 LQFP44 LQFP32/ SDIP32 VFQFPN32/ UFQFPN32 PE6/ AIN9 PE5/SPI_ NSS PC1/ TIM1_ CH1/ UAR T2_CK PC2/ TIM1_ CH2 28 ...

  • Page 28

    Pinout and pin description Pin number Pin name LQFP48 LQFP44 LQFP32/ SDIP32 VFQFPN32/ UFQFPN32 PD0/ TIM3_ CH2 [TIM1_ BKIN] [CLK_ CCO PD1/ SWIM PD2/ TIM3_ CH1 [TIM2_ CH3] ...

  • Page 29

    STM8S105xx Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016). DocID14771 Rev 10 Pinout and pin description 29/127 ...

  • Page 30

    Memory and register map 6 Memory and register map 6.1 Memory map The following table lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. 30/127 Figure 7: ...

  • Page 31

    STM8S105xx Table 7: Flash, Data EEPROM and RAM boundary addresses Memory area Flash program memory RAM Data EEPROM 6.2 Register map 6.2.1 I/O port hardware register map Address Block 0x00 5000 Port A 0x00 5001 0x00 5002 0x00 5003 0x00 ...

  • Page 32

    Memory and register map Address Block 0x00 500A Port C 0x00 500B 0x00 500C 0x00 500D 0x00 500E 0x00 500F Port D 0x00 5010 0x00 5011 0x00 5012 0x00 5013 0x00 5014 Port E 0x00 5015 0x00 5016 0x00 5017 ...

  • Page 33

    STM8S105xx Address Block 0x00 501D 0x00 501E Port G 0x00 501F 0x00 5020 0x00 5021 0x00 5022 0x00 5023 Port H 0x00 5024 0x00 5025 0x00 5026 0x00 5027 0x00 5028 Port I 0x00 5029 0x00 502A 0x00 502B 0x00 ...

  • Page 34

    Memory and register map 6.2.2 General hardware register map Address 0x00 5050 to 0x00 5059 0x00 505A 0x00 505B 0x00 505C 0x00 505D 0x00 505E 0x00 505F 0x00 5060 to 0x00 5061 0x00 5062 0x00 5063 0x00 5064 0x00 5065 ...

  • Page 35

    STM8S105xx Address 0x00 50A2 to 0x00 50B2 0x00 50B3 0x00 50B4 to 0x00 50BF 0x00 50C0 0x00 50C1 0x00 50C2 0x00 50C3 0x00 50C4 0x00 50C5 0x00 50C6 0x00 50C7 0x00 50C8 0x00 50C9 0x00 50CA 0x00 50CB 0x00 50CC ...

  • Page 36

    Memory and register map Address 0x00 50CE to 0x00 50D0 0x00 50D1 0x00 50D2 0x00 50D3 to 0x00 50DF 0x00 50E0 0x00 50E1 0x00 50E2 0x00 50E3 to 0x00 50EF 0x00 50F0 0x00 50F1 0x00 50F2 0x00 50F3 0x00 50F4 ...

  • Page 37

    STM8S105xx Address 0x00 5204 0x00 5205 0x00 5206 0x00 5207 0x00 5208 to 0x00 520F 0x00 5210 0x00 5211 0x00 5212 0x00 5213 0x00 5214 0x00 5215 0x00 5216 0x00 5217 0x00 5218 0x00 5219 0x00 521A 0x00 521B 0x00 ...

  • Page 38

    Memory and register map Address 0x00 521E 0x00 521F to 0x00 522F 0x00 5230 to 0x00 523F 0x00 5240 0x00 5241 0x00 5242 0x00 5243 0x00 5244 0x00 5245 0x00 5246 0x00 5247 0x00 5248 0x00 5249 0x00 524A 0x00 ...

  • Page 39

    STM8S105xx Address 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A 0x00 525B 0x00 525C 0x00 525D 0x00 525E 0x00 525F 0x00 5260 0x00 5261 Block Register label Register name TIM1_SMCR ...

  • Page 40

    Memory and register map Address 0x00 5262 0x00 5263 0x00 5264 0x00 5265 0x00 5266 0x00 5267 0x00 5268 0x00 5269 0x00 526A 0x00 526B 0x00 526C 0x00 526D 0x00 526E 0x00 526F 0x00 5270 to 0x00 52FF 0x00 5300 ...

  • Page 41

    STM8S105xx Address 0x00 5301 0x00 5302 0x00 5303 0x00 5304 0x00 5305 0x00 5306 0x00 5307 0x00 5308 0x00 5309 0x00 530A 0x00 530B 0x00 530C 0x00 530D 0x00 530E 0x00 530F 0x00 5310 Block Register label Register name TIM2_IER ...

  • Page 42

    Memory and register map Address 0x00 5311 0x00 5312 0x00 5313 0x00 5314 0x00 5315 to 0x00 531F 0x00 5320 0x00 5321 0x00 5322 0x00 5323 0x00 5324 0x00 5325 0x00 5326 0x00 5327 0x00 5328 0x00 5329 0x00 532A ...

  • Page 43

    STM8S105xx Address 0x00 532B 0x00 532C 0x00 532D 0x00 532E 0x00 532F 0x00 5330 0x00 5331 to 0x00 533F 0x00 5340 0x00 5341 0x00 5342 0x00 5343 0x00 5344 0x00 5345 0x00 5346 0x00 5347 to 0x00 53DF 0x00 53E0 ...

  • Page 44

    Memory and register map Address 0x00 53F4 to 0x00 53FF 0x00 5400 0x00 5401 0x00 5402 0x00 5403 0x00 5404 0x00 5405 0x00 5406 0x00 5407 0x00 5408 0x00 5409 0x00 540A 0x00 540B 0x00 540C 0x00 540D 44/127 Block ...

  • Page 45

    STM8S105xx Address 0x00 540E 0x00 540F 0x00 5410 to 0x00 57FF (1) Depends on the previous reset source. (2) Write only register. 6.2.3 CPU/SWIM/debug module/interrupt controller registers Table 10: CPU/SWIM/debug module/interrupt controller registers Address Block 0x00 7F00 CPU 0x00 7F01 ...

  • Page 46

    Memory and register map Address Block 0x00 7F0A 0x00 7F0B to Reserved area (85 bytes) 0x00 7F5F 0x00 7F60 CPU 0x00 7F70 ITC 0x00 7F71 0x00 7F72 0x00 7F73 0x00 7F74 0x00 7F75 0x00 7F76 0x00 7F77 0x00 7F78 to ...

  • Page 47

    STM8S105xx Address Block 0x00 7F93 0x00 7F94 0x00 7F95 0x00 7F96 0x00 7F97 0x00 7F98 0x00 7F99 0x00 7F9A 0x00 7F9B to Reserved area (5 bytes) 0x00 7F9F (1) Accessible by debug module only Register label Register name DM_BK2RE DM ...

  • Page 48

    Interrupt vector mapping 7 Interrupt vector mapping IRQ Source no. block RESET TRAP 0 TLI 1 AWU 2 CLK 3 EXTI0 4 EXTI1 5 EXTI2 6 EXTI3 7 EXTI4 SPI 11 TIM1 12 TIM1 13 TIM 14 ...

  • Page 49

    STM8S105xx IRQ Source no. block 15 TIM3 16 TIM3 UART2 21 UART2 22 ADC1 23 TIM 24 Flash Reserved (1) Except PA1 Description Wakeup from halt mode Update/ overflow - Capture/ compare - ...

  • Page 50

    Option bytes 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each ...

  • Page 51

    STM8S105xx Addr. Option Option Option bits name byte no. 7 NOPT6 0x480C Reserved OPT7 0x480D Reserved Reserved NOPT7 0x480E Reserved OPTBL 0x487E Bootloader BL[7:0] NOPTBL 0x487F NBL[7:0] Option byte no. OPT0 OPT1 OPT2 OPT3 Table 13: ...

  • Page 52

    Option bytes Option byte no. OPT4 OPT5 52/127 Description LSI_EN:Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source IWDG_HW: Independent watchdog 0: IWDG Independent watchdog ...

  • Page 53

    STM8S105xx Option byte no. OPT6 OPT7 OPTBL Table 14: Description of alternate function remapping bits [7:0] of OPT2 Option byte no. OPT2 Description Reserved Reserved BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM ...

  • Page 54

    Option bytes Option byte no. (1) Do not use more than one remapping option in the same port. (2) Refer to pinout description. 54/127 (1) Description 0: AFR2 remapping option inactive: Default alternate function 1: Port D0 alternate function = ...

  • Page 55

    STM8S105xx 9 Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. ...

  • Page 56

    Electrical characteristics 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

  • Page 57

    STM8S105xx 10.1.5 Loading capacitor The loading conditions used for pin parameter measurement are shown in the following figure. 10.1.6 Pin input voltage The input voltage measurement on a pin of the device is described in the following figure. 10.2 Absolute ...

  • Page 58

    Electrical characteristics Symbol Ratings Input voltage on any other pin |V - Variations between different power pins DDx Variations between all the different ground pins SSx SS V Electrostatic discharge voltage ESD (1) ...

  • Page 59

    STM8S105xx Symbol Ratings (4) (5) I INJ(PIN) (4) ΣI INJ(PIN) (1) Data based on characterization results, not tested in production. (2) All power (V DD connected to the external supply. (3) I/O pins used simultaneously for high current source/sink must ...

  • Page 60

    Electrical characteristics Symbol f CPU DD_IO VCAP ( (1) Care should be taken when selecting the capacitor, due to its tolerance, as well as its dependency on temperature, DC bias ...

  • Page 61

    STM8S105xx (2) To calculate P characteristics ) with the value for T given in Thermal (3) Refer to Thermal ( given by the test limit. Above this value the product behavior is not guaranteed. Jmax Functionality not guaranteed ...

  • Page 62

    Electrical characteristics 10.3.1 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor C V pin specified in the Operating conditions section. Care should be taken to limit CAP EXT the series inductance to ...

  • Page 63

    STM8S105xx Symbol Parameter I DD(RUN) Supply current in run mode, code executed fromFlash (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. Table 22: Total current consumption with code execution ...

  • Page 64

    Electrical characteristics Symbol Parameter mode, code executed from RAM Supply current in run mode, code executed from Flash 64/127 Conditions HSE user ext. clock (16 MHz) HSI RC osc. (16 MHz /128 HSE user ext. clock CPU ...

  • Page 65

    STM8S105xx Symbol Parameter (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. 10.3.2.2 Total current consumption in wait mode Table 23: Total current consumption in wait mode at V Symbol ...

  • Page 66

    Electrical characteristics Table 24: Total current consumption in wait mode at V Symbol Parameter I Supply DD(WFI) current in wait mode (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. ...

  • Page 67

    STM8S105xx Symbol Parameter (1) Data based on characterization results, not tested in production (2) Configured by the REGAH bit in the CLK_ICKR register. (3) Configured by the AHALT bit in the FLASH_CR1 register. Table 26: Total current consumption in active ...

  • Page 68

    Electrical characteristics Symbol Parameter (1) Data based on characterization results, not tested in production. (2) Configured by the REGAH bit in the CLK_ICKR register. (3) Configured by the AHALT bit in the FLASH_CR1 register. 10.3.2.4 Total current consumption in halt ...

  • Page 69

    STM8S105xx Table 28: Total current consumption in halt mode at V Symbol Parameter I Supply current DD(H) in halt mode (1) Data based on characterization results, not tested in production. 10.3.2.5 Low power mode wakeup times Symbol Parameter Wakeup time ...

  • Page 70

    Electrical characteristics Symbol Parameter (3) mode (1) Data guaranteed by design, not tested in production 1/f WU(WFI) master (3) Measured from interrupt event to interrupt vector fetch. (4) Configured by the ...

  • Page 71

    STM8S105xx Symbol Parameter I TIM3 timer supply current DD(TIM3) I TIM4 timer supply current DD(TIM4) I UART2 supply current DD(UART2) I SPI supply current DD(SPI DD ADC1 supply current when converting DD(ADC1) (1) Data ...

  • Page 72

    Electrical characteristics Figure 14: Typ. I Figure 15: Typ. I 72/127 vs. f HSE user external clock, V DD(RUN) CPU , vs. V HSI RC osc, f DD(RUN DocID14771 Rev 10 STM8S105xx = ...

  • Page 73

    STM8S105xx Figure 16: Typ. I Figure 17: Typ. I vs. V HSE user external clock, f DD(WFI vs HSE user external clock V DD(WFI) CPU DocID14771 Rev 10 Electrical characteristics = 16 MHz CPU = 5 ...

  • Page 74

    Electrical characteristics Figure 18: Typ. I 10.3.3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for V Table 32: HSE user external clock characteristics Symbol Parameter f User external clock source HSE_ext frequency ...

  • Page 75

    STM8S105xx V HSEH V HSEL HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external ...

  • Page 76

    Electrical characteristics (2) The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R value. Refer to crystal manufacturer for more details m (3) Data based on characterization results, not tested in ...

  • Page 77

    STM8S105xx Symbol Parameter ACC Accuracy of HSI HSI oscillator Accuracy of HSI oscillator (factory calibrated) t HSI oscillator su(HSI) wakeup time including calibration I HSI oscillator power DD(HSI) consumption (1) Refer to application note. (2) Guaranteed by design, not tested ...

  • Page 78

    Electrical characteristics Figure 22: Typical HSI accuracy vs V Low speed internal RC oscillator (LSI) Subject to general operating conditions for V Symbol Parameter f Frequency LSI t LSI oscillator wakeup time su(LSI) I LSI oscillator power consumption DD(LSI) (1) ...

  • Page 79

    STM8S105xx Figure 23: Typical LSI accuracy vs V 10.3.5 Memory characteristics RAM and hardware registers Symbol Parameter V Data retention mode RM (1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset ...

  • Page 80

    Electrical characteristics Symbol Parameter Fast programming time for 1 block (128 bytes) t Erase time for 1 block (128 bytes) erase N Erase/write cycles RW memory) Erase/write cycles(data memory) t Data retention (program memory) RET after 10k erase/write cycles at ...

  • Page 81

    STM8S105xx Symbol Parameter V Input high level IH voltage V Hysteresis hys R Pull-up resistor Rise and fall R F time( Input leakage lkg current, analog and digital I Analog input ...

  • Page 82

    Electrical characteristics Figure 25: Typical pull-up resistance vs V Figure 26: Typical pull-up current The pull- pure resistor (slope goes through 0). Symbol Parameter V Output low level with four pins OL sunk 82/127 Table ...

  • Page 83

    STM8S105xx Symbol Parameter Output low level with eight pins sunk V Output high level with four OH pins sourced Output high level with eight pins sourced (1) Data based on characterization results, not tested in production Table 40: Output driving ...

  • Page 84

    Electrical characteristics Symbol Parameter Output high level with eight pins sourced Output high level with four pins sourced (1) Data based on characterization results, not tested in production 10.3.7 Typical output level curves The following figures show typical output level ...

  • Page 85

    STM8S105xx Figure 29: Typ. V Figure 28: Typ 3.3 V (standard ports (true open drain ports DocID14771 Rev 10 Electrical characteristics 85/127 ...

  • Page 86

    Electrical characteristics Figure 30: Typ. V 86/127 @ V = 3.3 V (true open drain ports Figure 31: Typ (high sink ports DocID14771 Rev 10 STM8S105xx ...

  • Page 87

    STM8S105xx Figure 32: Typ Figure 33: Typ DocID14771 Rev 10 Electrical characteristics = 3.3 V (high sink ports (standard ports) DD 87/127 ...

  • Page 88

    Electrical characteristics Figure 34: Typ. V Figure 35: Typ. V 88/127 - 3.3 V (standard ports (high sink ports DocID14771 Rev 10 STM8S105xx ...

  • Page 89

    STM8S105xx Figure 36: Typ. V 10.3.8 Reset pin characteristics Subject to general operating conditions for V Symbol Parameter V IL(NRST) NRST input low (1) level voltage V IH(NRST) NRST input high level voltage V OL(NRST) NRST output low level voltage ...

  • Page 90

    Electrical characteristics Symbol Parameter t OP(NRST) NRST output (3) pulse (1) Data based on characterization results, not tested in production. (2) The R pull-up equivalent resistor is based on a resistive transistor PU (3) Data guaranteed by design, not tested ...

  • Page 91

    STM8S105xx Figure 38: Typical NRST pull-up resistance vs V Figure 39: Typical NRST pull-up current vs V The reset network shown in the following figure protects the device against parasitic resets. The user must ensure that the level on the ...

  • Page 92

    Electrical characteristics External reset circuit (optional) 10.3.9 SPI serial peripheral interface Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature 1/f MASTER MASTER Refer to I/O port characteristics ...

  • Page 93

    STM8S105xx Symbol Parameter (1) t Data input hold h(MI) time (1) t h(SI) Data input hold time (1) (2) t Data output a(SO) access time (1) (3) t Data output dis(SO) disable time (1) t Data output v(SO) valid time ...

  • Page 94

    Electrical characteristics Figure 41: SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 t a(SO) MISO OUT P UT MOSI I NPUT Figure 42: SPI timing diagram - slave ...

  • Page 95

    STM8S105xx NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO INP UT MOSI OUTUT 1. Measurement points are made at CMOS levels: 0 10.3. interface characteristics Symbol Parameter t SCL clock low ...

  • Page 96

    Electrical characteristics Symbol Parameter t START condition hold time h(STA) t Repeated START condition su(STA) setup time t STOP condition setup time su(STO) t STOP to START condition time w(STO:STA) (bus free) C Capacitive load for each bus line b ...

  • Page 97

    STM8S105xx 10.3.11 10-bit ADC characteristics Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Analog supply DDA V Positive reference voltage REF+ V Negative reference voltage REF- V Conversion voltage range AIN C Internal ...

  • Page 98

    Electrical characteristics changes of the analog input voltage have no effect on the conversion result. Values for the sample clock t S Symbol Parameter |E | Total unadjusted error Offset error Gain error G ...

  • Page 99

    STM8S105xx Any positive injection current within the limits specified for I port pin characteristics section does not affect the ADC accuracy. Table 47: ADC accuracy with R Symbol Parameter |E | Total unadjusted error Offset error O ...

  • Page 100

    Electrical characteristics 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line E = Total unadjusted error: maximum deviation between the actual and the ideal transfer T curves Offset error: deviation ...

  • Page 101

    STM8S105xx 10.3.12.1 Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). • FESD: Functional electrostatic discharge (positive and ...

  • Page 102

    Electrical characteristics Symbol Parameter and V SS functional disturbance (1) Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 (EMC guidelines for STM8S microcontrollers). 10.3.12.3 Electromagnetic interference (EMI) Emission tests conform to the IEC61967-2 standard for ...

  • Page 103

    ... Parameter LU Static latch-up class (1) Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). Table 50: ESD absolute maximum ratings ...

  • Page 104

    Package information 11 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...

  • Page 105

    STM8S105xx Dim. mm Min D1 6.800 D3 E 8.800 E1 6.800 0.450 L1 k 0° ccc (1) Values in inches are converted from mm and rounded to 4 decimal digits inches Typ Max Min 7.000 7.200 0.2677 ...

  • Page 106

    Package information 11.2 44-pin LQFP package mechanical data Pin 1 identification Table 53: 44-pin low profile quad flat package mechanical data Dim. mm Min A A1 0.050 A2 1.350 b 0.300 c 0.090 D 11.800 D1 9.800 ...

  • Page 107

    STM8S105xx Dim. mm Min E1 9.800 0.450 L1 k 0.0° ccc (1) Values in inches are converted from mm and rounded to 4 decimal digits 11.3 32-pin LQFP package mechanical data Pin 1 ...

  • Page 108

    Package information Table 54: 32-pin low profile quad flat package mechanical data Dim. mm Min A A1 0.050 A2 1.350 b 0.300 c 0.090 D 8.800 D1 6.800 D3 E 8.800 E1 6.800 0.450 L1 k 0° ...

  • Page 109

    STM8S105xx 11.4 32-lead VFQFPN package mechanical data Figure 50: 32-lead very thin fine pitch quad flat no-lead package ( There is an exposed die pad on the underside of the VFQFPN package recommended to connect ...

  • Page 110

    Package information Dim. mm Min D2 3.20 E 4. 0.30 ddd (1) Values in inches are converted from mm and rounded to 4 decimal digits. 110/127 inches Typ Max Min 3.45 3.70 0.1260 5.00 5.15 0.1909 ...

  • Page 111

    STM8S105xx 11.5 32-lead UFQFPN package mechanical data Figure 51: 32-lead, ultra thin, fine pitch quad flat no-lead package ( Drawing is not to scale. 2. All leads/pads should be soldered to the PCB to improve the lead/pad ...

  • Page 112

    Package information Dim. mm Min D 4.850 D2 3.200 E 4.850 E2 3.200 e L 0.300 ddd (1) Values in inches are converted from mm and rounded to 4 decimal digits. 11.6 SDIP32 package mechanical data Table 57: 32-lead shrink ...

  • Page 113

    STM8S105xx Dim. mm Min A1 0.508 A2 3.048 B 0.356 B1 0.762 C 0.203 D 27.430 E 9.906 E1 7.620 2.540 (1) Values in inches are converted from mm and rounded to 4 decimal digits inches ...

  • Page 114

    Thermal characteristics 12 Thermal characteristics The maximum chip junction temperature (T Operating conditions The maximum chip-junction temperature, T the following equation Jmax Amax Where: • the maximum ambient temperature in °C Amax • ...

  • Page 115

    STM8S105xx 12.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code. The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions: ...

  • Page 116

    Ordering information 13 Ordering information Figure 53: STM8S105xx access line ordering information scheme Example: Product class Family type S = Standard Sub-family type 105 = access line STM8S105x Pin count pins pins C = ...

  • Page 117

    ... FASTROM code name is assigned by STMicroelectronics. ............................................................................................. ............................................................................................. a ............................................................................................. 16 Kbyte [ ] STM8S105K4 [ ] STM8S105K4 [ ] STM8S105S4 [ ] STM8S105C4 Fixed value TRAP instruction opcode Illegal opcode (causes a reset when executed) DocID14771 Rev 10 Ordering information 32 Kbyte [ ] STM8S105K6 [ ] STM8S105K6 [ ] STM8S105S6 [ ] STM8S105C6 ...

  • Page 118

    Ordering information UBC, bit0 UBC bit1 UBC bit2 UBC bit3 UBC bit4 UBC bit5 OPT2 alternate function remapping AFR0 (check only one option) AFR1 (check only one option) AFR2 (check only one option) AFR3 (check only one option) AFR4 (check ...

  • Page 119

    STM8S105xx AFR5 (check only one option) AFR6 (check only one option) AFR7 (check only one option) OPT3 watchdog WWDG_HALT (check only one option) WWDG_HW (check only one option) IWDG_HW (check only one option) LSI_EN (check only one option) HSITRIM (check ...

  • Page 120

    Ordering information EXTCLK (check only one option) OPT5 crystal oscillator stabilization HSECNT (check only one option 2048 HSE cycles [ ] 128 HSE cycles [ ] 8 HSE cycles [ ] 0.5 HSE cycles OPT6 is reserved OPT7 ...

  • Page 121

    ... In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. ...

  • Page 122

    STM8 development tools 14.2.1 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST Visual Develop – Full-featured integrated development environment from ST, featuring • Seamless ...

  • Page 123

    STM8S105xx 15 Revision history Date Revision 05-Jun-2008 1 23-Jun-2008 2 12-Aug-2008 3 17-Sep-2008 4 05-Feb-2009 5 27-Feb-2009 6 12-May-2009 7 Table 59: Document revision history Changes Initial release. Corrected number of high sink outputs I/Os on Features. ...

  • Page 124

    Revision history Date Revision 10-Jun-2009 8 21-Apr-2010 9 124/127 Changes Added Table 5 on page 22 . Updated Auto wakeup counter. Updated pins 25, 30, and 31 in Removed Table 7: Pin-to-pin comparison of pin 32-pin ...

  • Page 125

    STM8S105xx Date Revision 21-Sep-2010 10 Changes Added Unique ID Operating conditions: added introductory text; removed low power dissipation condition for T and added ESR and ESL data in table "general operating conditions". Total current consumption in halt ...

  • Page 126

    Revision history Date Revision 126/127 Changes Updated Figure 44: Typical application with I2C bus and timing diagram (1) . Updated footnote 1 in Table 46: ADC accuracy with RAIN < 10 kΩ , VDDA and Table 47: ADC ...

  • Page 127

    ... ST and the ST logo are trademarks or registered trademarks various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel ...