STM8AF6248 STMicroelectronics, STM8AF6248 Datasheet - Page 90

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STM8AF6248

Manufacturer Part Number
STM8AF6248
Description
STM8AF62 Standard Line
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM8AF6248

Max Fcpu
16 MHz
Flash Program Memory
16 to 32 Kbytes Flash; data retention 20 years at 55 °C after 1 kcycle
Data Memory
0.5 to 1 Kbyte true data EEPROM; endurance 300 kcycles
Ram
1 to 2 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

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Revision history
90/91
Table 52.
31-Jan-2011
Date
Document revision history (continued)
(continued)
Revision
5
Renamed Fast Active Halt mode to Active-halt mode with regulator
on, and Slow Active Halt mode to Active-halt mode with regulator off.
Updated
modes. General conditions for VDD apply, TA = -40 to 55
particular I
t
Removed I
consumption VDD = 5.0
Updated general conditions in
characteristics. Modified T
program memory
Update I
Table 37: I/O static
Added t
characteristics. Added recommendations concerning NRST pin level
above
external capacitor value.
Added Raisonance compiler in
Moved know limitations to separate errata sheet.
WU(SAH)
Doc ID 14952 Rev 5
Figure 36: Recommended reset pin
IFP(NRST)
lkg ana
renamed t
Table 26: Total current consumption in Halt and Active-halt
DD(FAH)
DD(USART)
maximum value for T
and renamed V
and
and I
WU(AH)
characteristics.
from
Table 36: Data
DD(SAH)
V.
, and temperature condition added.
WE
Table 29: Typical peripheral current
Changes
maximum value in
Section 10.3.5: Memory
Section 13.2: Software
renamed I
F(NRST)
A
STM8AF61xx, STM8AF62xx
memory.
ranging from −40 to 150 °C in
t
IFP
DD(AH)
protection, and updated
in
Table 38: NRST pin
; t
Table 35: Flash
WU(FAH)
tools.
°C, in
and

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