STR911FAW42 STMicroelectronics, STR911FAW42 Datasheet - Page 23

• Manufacturer Part Number: STR911FAW42
• Description: 32-bit MCU
• Manufacturer: STMicroelectronics

Specifications of STR911FAW42

• Arm966e-s Risc Core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

STR91xFAxxx
3.10.11
3.11
3.11.1
Operation example
As an example of CCU operation, a 25 MHz crystal can be connected to the main oscillator
input on pins X1_CPU and X2_CPU, a 32.768 kHz crystal connected to pins X1_RTC and
X2_RTC, and the clock input of an external Ethernet PHY device is connected to STR91xFA
output pin P5.2. In this case, the CCU can run the CPU at 96 MHz from PLL, the USB
interface at 48 MHz, and the Ethernet interface at 25 MHz. The RTC is always running in the
background at 32.768 kHz, and the CPU can go to very low power mode dynamically by
running from 32.768 kHz and shutting off peripheral clocks and the PLL as needed.
Flexible power management
The STR91xFA offers configurable and flexible power management control that allows the
user to choose the best power option to fit the application. Power consumption can be
dynamically managed by firmware and hardware to match the system’s requirements.
Power management is provided via clock control to the CPU and individual peripherals.
Clocks to the CPU and peripherals can be individually divided and gated off as needed. In
addition to individual clock divisors, the CCU master clock source going to the CPU, AHB,
APB, EMI, and FMI can be divided dynamically by as much as 1024 for low power operation.
Additionally, the CCU may switch its input to the 32.768 kHz RTC clock at any time for low
power.
The STR91xFA supports the following three global power control modes:
●
●
●
A special mode is used when JTAG debug is active which never gates off any clocks even if
the CPU enters Idle or Sleep mode.
Run mode
This is the default mode after any reset occurs. Firmware can gate off or scale any individual
clock. Also available is a special Interrupt Mode which allows the CPU to automatically run
full speed during an interrupt service and return back to the selected CPU clock divisor rate
when the interrupt has been serviced. The advantage here is that the CPU can run at a very
low frequency to conserve power until a periodic wake-up event or an asynchronous
interrupt occurs at which time the CPU runs full speed immediately.
Run Mode: All clocks are on with option to gate individual clocks off via clock mask
registers.
Idle Mode: CPU and FMI clocks are off until an interrupt, reset, or wake-up occurs.
Pre-configured clock mask registers selectively allow individual peripheral clocks to
continue run during Idle Mode.
Sleep Mode: All clocks off except RTC clock. Wake up unit remains powered, PLL is
forced off.
Doc ID 13495 Rev 6
Functional overview
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