STR912FAZ42 STMicroelectronics, STR912FAZ42 Datasheet - Page 74

• Manufacturer Part Number: STR912FAZ42
• Description: 32-bit MCU
• Manufacturer: STMicroelectronics

Specifications of STR912FAZ42

• Arm966e-s Risc Core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

Electrical characteristics
7.9.5
7.9.6
7.9.7
74/102
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up
performance.
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This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations:
The software flowchart must include the management of runaway conditions such as:
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Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electrical sensitivity
Table 30.
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
Symbol
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
LU
A supply overvoltage (applied to each power supply pin) and
A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Static latch-up class
Static latch-up data
Parameter
Doc ID 13495 Rev 6
T
A
= +25 °C conforming to JESD78A
Conditions
STR91xFAxxx
II class A
Class
(1)