DS1350W Maxim, DS1350W Datasheet - Page 2

• Manufacturer Part Number: DS1350W
• Description: The DS1350W 3
• Manufacturer: Maxim

READ MODE
The DS1350W executes a read cycle whenever
Enable) and
(A
eight data output drivers within t
that
satisfied, then data access must be measured from the later occurring signal (
parameter is either t
WRITE MODE
The DS1350W executes a write cycle whenever the
address inputs are stable. The later occurring falling edge of
write cycle. The write cycle is terminated by the earlier rising edge of
be kept valid throughout the write cycle.
(t
write cycles to avoid bus contention. However, if the output drivers are enabled (
DATA RETENTION MODE
The DS1350W provides full functional capability for V
volts. Data is maintained in the absence of V
static RAMs constantly monitor V
write protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As V
falls below approximately 2.5 volts, the power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when V
switching circuit connects external V
RAM operation can resume after V
SYSTEM POWER MONITORING
The DS1350W has the ability to monitor the external V
supply condition is detected, the NV SRAM warns a processor-based system of impending power failure
by asserting
during power-on transients and to allow t
BATTERY MONITORING
The DS1350W automatically performs periodic battery voltage monitoring on a 24-hour time interval.
Such monitoring begins within t
occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1 MΩ test resistor for 1
second. During this 1 second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output
The battery is still retested after each V
is found to be higher than 2.6V during such testing,
resumes.
WE
WR
0
- A
) before another cycle can be initiated. The
will disable the outputs in t
CE
18
) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the
and
BW
OE
RST
OE
has an open-drain output driver.
(Output Enable) are active (low). The unique address specified by the 19 address inputs
. On power-up,
(Output Enable) access times are also satisfied. If
CO
for
BW
CE
is asserted. Once asserted,
or t
ODW
ACC
OE
REC
CC
RST
CC
from its falling edge.
for
(Access Time) after the last address input signal is stable, providing
. Should the supply voltage decay, the NV SRAMs automatically
CC
exceeds 3.0 volts.
after V
CC
OE
is held active for 200 ms nominal to prevent system operation
to the RAM and disconnects the lithium energy source. Normal
REC
WE
power-up, however, even if
rather than address access.
to elapse.
CC
CC
must return to the high state for a minimum recovery time
without any additional support circuitry. The nonvolatile
rises above V
2 of 10
OE
WE
CC
WE
control signal should be kept inactive (high) during
rises above approximately 2.5 volts, the power
RST
CC
(Write Enable) is inactive (high) and
CC
BW
and
BW
power supply. When an out-of-tolerance power
greater than 3.0 volts and write protects by 2.8
has an open-drain output driver.
remains active until the module is replaced.
CE
is de-asserted and regular 24-hour testing
CE
TP
signals are in the active (low) state after
and is suspended when power failure
or
CE
WE
BW
OE
or
will determine the start of the
is active. If the battery voltage
and
WE
CE
CE
. All address inputs must
or
CE
access times are not
OE
and
) and the limiting
OE
active) then
CE
DS1350W
(Chip
CC