DS28E01-100 Maxim, DS28E01-100 Datasheet
DS28E01-100
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DS28E01-100 Summary of contents
Page 1
... All memory pages can be write protected, and one page can be put in EPROM-emulation mode, where bits can only be changed from state. Each DS28E01-100 has its own guaranteed unique 64-bit ROM registration num- ber that is factory lasered into the chip. The DS28E01- ...
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... Storage Temperature Range .............................-55°C to +125°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Note 12: Applies to a single device attached to a 1-Wire line. Note 13: The earliest recognition of a negative edge is possible at t Note 14: Defines maximum possible bit rate. Equal to t Note 15: Interval after t during which a bus master is guaranteed to sample a logic there is a DS28E01-100 present. RSTL Minimum limit maximum limit is t PDHMAX Note 16: Numbers in bold are not in compliance with legacy 1-Wire product standards ...
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... V . The actual ε, respectively W0LMAX F to the input-high RLMAX F DS28E01-100 VALUES STANDARD SPEED OVERDRIVE SPEED (μs) (μs) MIN MAX MIN 65* (undefined) 8* (undefined) 480 640 240 8 60 120 6 MAX ...
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... MAC. The SHA-1 engine is also activated to compute 160-bit MACs when performing an authenti- cated read of a memory page and when computing a new secret, instead of loading it. The DS28E01-100 understands a unique command “Refresh Scratchpad.” Proper use of a refresh sequence after a Copy Scratchpad operation reduces the number of weak bit failures if the device is used in a touch environment (see the Writing with Verification section) ...
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... MEMORY 64 BITS shift register contains the CRC value. Shifting in the 8 bits of the CRC returns the shift register to all 0s. The DS28E01-100 has four memory areas: data memo- ry, secrets memory, register page with special function registers and user bytes, and a volatile scratchpad. The data memory is organized as four pages of 32 bytes ...
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... STAGE Figure 4. 1-Wire CRC Generator _______________________________________________________________________________________ 1Kb Protected 1-Wire EEPROM DS28E01-100 DATA FIELD AFFECTED: 64-BIT REG. #, RC-FLAG 64-BIT REG. #, RC-FLAG 64-BIT REG. #, RC-FLAG RC-FLAG RC-FLAG RC-FLAG, OD-FLAG 64-BIT REG. #, RC-FLAG, OD-FLAG Refer to the full data sheet. 48-BIT SERIAL NUMBER ...
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... Register E read-only transfer-status register used to verify data integrity with write commands. Since the scratch- pad of the DS28E01-100 is designed to accept data in blocks of 8 bytes only, the lower 3 bits of TA1 are _______________________________________________________________________________________ 1Kb Protected 1-Wire EEPROM Refer to the full data sheet ...
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... The authorization-accepted (AA) flag (bit 7 of the E/S register) is normally cleared by a Write Scratchpad or Refresh Scratchpad; therefore set indicates that the DS28E01-100 did not under- stand the proceeding Write (or Refresh) Scratchpad command. In either of these cases, the master should rewrite the scratchpad. After the master receives the E/S register, the scratchpad data is received ...
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ABRIDGED DATA SHEET Memory and SHA-1 Function This section describes the commands and flowcharts needed to use the memory and SHA-1 engine of the device. Refer to the full data sheet for more information. ______________________________________________________________________________________ 1Kb Protected 1-Wire EEPROM with ...
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ABRIDGED DATA SHEET 1Kb Protected 1-Wire EEPROM ______________________________________________________________________________________ with SHA-1 Engine SHA-1 Computation Algorithm This description of the SHA-1 computation is adapted from the Secure Hash Standard SHA-1 document from the National Institute of Standards and Technology (NIST). Refer to ...
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... The 1-Wire port of the DS28E01- 100 is open drain with an internal circuit equivalent to that shown in Figure 9. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS28E01-100 supports both a standard and overdrive communication speed of 15.3kbps (max) and 125kbps (max), respectively. Note V ...
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... The presence pulse lets the bus master know that the DS28E01-100 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. 1-Wire ROM Function ...
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... COMMAND DS28E01-100 Tx BIT 0 MASTER Tx BIT 0 DS28E01-100 Tx BIT 0 MASTER Tx BIT BIT 0 MATCH? BIT 0 MATCH DS28E01-100 Tx BIT 1 MASTER Tx BIT 1 DS28E01-100 Tx BIT 1 MASTER Tx BIT BIT 1 MATCH? BIT 1 MATCH DS28E01-100 Tx BIT 63 MASTER Tx BIT 63 DS28E01-1001 Tx BIT 63 MASTER Tx BIT ...
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ABRIDGED DATA SHEET TO FIGURE 10a FROM FIGURE 10a FROM FIGURE 10a TO FIGURE 10a Figure 10b. ROM Functions Flowchart (continued) ______________________________________________________________________________________ 1Kb Protected 1-Wire EEPROM with SHA-1 Engine A5h 3Ch N N RESUME OVERDRIVE- COMMAND? SKIP ROM ...
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... Figure 11 shows the initialization sequence required to begin any communication with the DS28E01-100. A reset pulse followed by a presence pulse indicates that the DS28E01-100 is ready to receive data, given the correct ROM and memory and SHA-1 function com- mand. If the bus master uses slew-rate control on the falling edge, it must pull down the line for t compensate for the edge ...
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... When responding with a 1, the DS28E01-100 does not hold the data line low at all, and the voltage starts rising as soon as t The sum of t ...
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... WRITE-ZERO TIME SLOT V PUP V IHMASTER ILMAX RESISTOR READ-DATA TIME SLOT PUP V IHMASTER ILMAX RESISTOR Figure 12. Read/Write Timing Diagrams 30 ______________________________________________________________________________________ ε t SLOT MASTER t W0L t SLOT MASTER t MSR MASTER SAMPLING WINDOW δ t SLOT MASTER ε t REC t REC DS28E01-100 ...
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... Devices that have the parameters V fied in their electrical characteristics use the improved 1-Wire front-end. The DS28E01-100 uses two different types of CRCs. One CRC is an 8-bit type that is computed at the factory and is stored in the most significant byte of the 64-bit registration number. The bus master can compute a ...
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... RoHS status only. Package drawings may show a different suffix character, but the drawing per- tains to the package regardless of RoHS status. PACKAGE TYPE 6 TSOC 2 SFN 6 TDFN-EP 2 TO-92 ______________________________________________________________________________________ 1Kb Protected 1-Wire EEPROM BOTTOM VIEW DS28E01-100 + N. N. N.C. ...
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... Maximum Ratings, Pin Description, Pin Configurations, and Package Information. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...