DS28E02 Maxim, DS28E02 Datasheet

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DS28E02

Manufacturer Part Number
DS28E02
Description
The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm (SHA-1)
Manufacturer
Maxim
Datasheet

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The DS28E02 combines 1024 bits of EEPROM with
challenge-and-response authentication security imple-
mented with the FIPS 180-3 Secure Hash Algorithm
(SHA-1). The 1024-bit EEPROM array is configured as
four pages of 256 bits with a 64-bit scratchpad to per-
form write operations. All memory pages can be write
protected, and one page can be put in EPROM-emula-
tion mode, where bits can only be changed from a 1 to
a 0 state. Each DS28E02 has its own guaranteed
unique 64-bit ROM registration number that is factory
installed into the chip. The DS28E02 communicates
over the single-contact 1-Wire
tion follows the standard 1-Wire protocol with the regis-
tration number acting as the node address in the case
of a multidevice 1-Wire network.
Rev 0: 6/10
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Reference Design License Management
System Intellectual Property Protection
Sensor/Accessory Authentication and Calibration
Medical Consumable Authentication
Printer Cartridge Configuration and Monitoring
V
CC
μC
Typical Operating Circuit
________________________________________________________________ Maxim Integrated Products
General Description
ABRIDGED DATA SHEET
R
PUP
®
bus. The communica-
IO
Applications
1-Wire SHA-1 Authenticated 1Kb
DS28E02
GND
EEPROM with 1.8V Operation
♦ 1024 Bits of EEPROM Memory Partitioned Into
♦ On-Chip 512-Bit SHA-1 Engine to Compute 160-
♦ Write Access Requires Knowledge of the Secret
♦ User-Programmable Page Write Protection for
♦ User-Programmable OTP EPROM Emulation Mode
♦ Communicates to Host with a Single Digital
♦ Switchpoint Hysteresis and Filtering to Optimize
♦ Reads and Writes Over 1.75V to 3.65V Voltage
♦ 6-Lead TSOC and TDFN Packages
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
* EP = Exposed pad.
DS28E02P+
DS28E02P+T&R
DS28E02Q+T&R
Four Pages of 256 Bits
Bit Message Authentication Codes (MACs) and to
Generate Secrets
and the Capability of Computing and Transmitting
a 160-Bit MAC as Authorization
Page 0, Page 3, or All Four Pages Together
for Page 1 (“Write to 0”)
Signal at 12.5kbps or 35.7kbps Using 1-Wire
Protocol
Communication Performance in the Presence of
Noise
Range from -20°C to +85°C
PART
-20°C to +85°C
-20°C to +85°C
-20°C to +85°C
TEMP RANGE
Ordering Information
PIN-PACKAGE
6 TSOC
6 TSOC
6 TDFN-EP*
(2.5k pcs)
Features
1

Related parts for DS28E02

DS28E02 Summary of contents

Page 1

... All memory pages can be write protected, and one page can be put in EPROM-emula- tion mode, where bits can only be changed from state. Each DS28E02 has its own guaranteed unique 64-bit ROM registration number that is factory installed into the chip. The DS28E02 communicates ® ...

Page 2

... Operating Temperature Range ...........................-20°C to +85°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...

Page 3

... Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired. Note 15: Interval after t during which a bus master is guaranteed to sample a logic there is a DS28E02 present. RSTL Note 16: ε in Figure 12 represents the time required for the pullup circuitry to pull the voltage from V maximum duration for the master to pull the line low is t Note 17: δ ...

Page 4

... After the data has been verified, a copy scratch- pad command transfers the data to its final memory location, provided that the DS28E02 receives a match- ing 160-bit MAC. The computation of the MAC involves the secret and additional data stored in the DS28E02 including the device’s registration number. The 4 _______________________________________________________________________________________ ...

Page 5

... The function protocols are described in Figure 8. All data is read and written least signifi- cant bit first. Each DS28E02 contains a unique ROM registration num- ber that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits ...

Page 6

... STAGE STAGE The DS28E02 has four memory areas: data memory, secrets memory, register page with special function registers and user bytes, and a volatile scratchpad. The data memory is organized as four pages of 32 bytes. LSB 8-BIT FAMILY CODE LSB MSB ...

Page 7

ABRIDGED DATA SHEET Figure 5. Memory Map _______________________________________________________________________________________ 1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation Refer to the full data sheet. 7 ...

Page 8

... Register E read- only transfer-status register used to verify data integrity with write commands. Since the scratchpad of the DS28E02 is designed to accept data in blocks of 8 bytes only, the lower 3 bits of TA1 are forced to 0 and 3 2 ...

Page 9

... TA1 and TA2 and sends the contents of the E/S register. The partial flag (bit 5 of the E/S register) is set the last data byte the DS28E02 received during a write scratchpad or refresh scratch- pad command was incomplete there was a loss of power since data was last written to the scratchpad ...

Page 10

ABRIDGED DATA SHEET 1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation Memory and SHA-1 Function This section describes the commands and flowcharts needed to use the memory and SHA-1 engine of the device. Refer to the full data sheet for ...

Page 11

... Bus System The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS28E02 is a slave device. The bus master is typically a microcon- troller. The discussion of this bus system is broken down into three topics: hardware configuration, trans- action sequence, and 1-Wire signaling (signal types and timing) ...

Page 12

... To facilitate this, each device attached to the 1-Wire bus must have open-drain or three-state outputs. The 1-Wire port of the DS28E02 is open drain with an internal circuit equivalent to that shown in Figure 9. A multidrop bus consists of a 1-Wire bus with multiple slaves attached ...

Page 13

... The presence pulse lets the bus master know that the DS28E02 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. 1-Wire ROM Function ...

Page 14

... COMMAND DS28E02 Tx BIT 0 MASTER Tx BIT 0 DS28E02 Tx BIT 0 MASTER Tx BIT BIT 0 MATCH? BIT 0 MATCH DS28E02 Tx BIT 1 MASTER Tx BIT 1 DS28E02 Tx BIT 1 MASTER Tx BIT BIT 1 MATCH? BIT 1 MATCH DS28E02 Tx BIT 63 MASTER Tx BIT 63 DS28E02 Tx BIT 63 MASTER Tx BIT ...

Page 15

ABRIDGED DATA SHEET 1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation TO FIGURE 10a FROM FIGURE 10a RESUME COMMAND FROM FIGURE 10a TO FIGURE 10a NOTE: THE OD FLAG REMAINS THE DEVICE WAS ALREADY ...

Page 16

... Resume [A5h] The Overdrive-Match ROM command followed by a 64- bit registration number transmitted at overdrive speed allows the bus master to address a specific DS28E02 on a multidrop bus and to simultaneously set it in overdrive mode. Only the DS28E02 that exactly matches the 64- bit number responds to the subsequent memory or SHA-1 function command ...

Page 17

... When responding with a 1, the DS28E02 does not hold the data line low at all, and the voltage starts rising as soon as t The sum of t ...

Page 18

... READ-DATA TIME SLOT PUP V IHMASTER ILMAX RESISTOR Figure 12. Read/Write Timing Diagrams ______________________________________________________________________________________ 1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation ε t SLOT MASTER t W0L t SLOT MASTER MSR MASTER SAMPLING WINDOW δ t SLOT MASTER ε t REC t REC DS28E02 29 ...

Page 19

... The bus master can compute a CRC value from the first 56 bits of the 64-bit registration num- ber and compare it to the value read from the DS28E02 to determine if the registration number has been received error-free. The equivalent polynomial function ...

Page 20

... ABRIDGED DATA SHEET For the latest package outline information and land patterns www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status ...

Page 21

... Initial release Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 34 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © ...

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