DS28E04-100 Maxim, DS28E04-100 Datasheet
DS28E04-100
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DS28E04-100 Summary of contents
Page 1
... EPROM- emulation mode, where bits can only be changed from state. In addition to the memory, the DS28E04-100 has two general-purpose I/O ports that can be used for input or to generate level and/or pulse outputs. Activity registers also capture port activity for state change monitoring ...
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... Lead Temperature (soldering, 10s) Soldering Temperature (reflow) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied ...
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... After V is crossed during a rising edge on IO, the voltage on IO has to drop by at least V TH Note 15: Applies to a single DS28E04-100 without V Note 16: The earliest recognition of a negative edge is possible at t Note 17: Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table. ...
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... The copy scratchpad command transfers the data to its final memory location. Each DS28E04-100 has a device ID number that is 64 bits long. The user can define seven bits of this number through address pins. The remaining 57 bits are factory-lasered into the chip. The device ID number guarantees unique identification and is used to address the device in a multidrop 1-Wire network environment, where multiple devices reside on a common 1-Wire bus and operate independently of each other ...
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... OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS28E04-100. The DS28E04-100 has five main data components: 1) 64-bit device ID number, 2) 32-byte scratchpad, 3) sixteen 32-byte pages of EEPROM, 4) Special Function Register, and 5) PIO Control Registers. The hierarchical structure of the 1-Wire protocol is shown in Figure 2 ...
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... Commands (see Figure 9) 64-BIT DEVICE ID NUMBER (NETWORK ADDRESS) Each DS28E04-100 has a unique device ID number that is 64 bits long, as shown in Figure 3. The first 8 bits are a 1-Wire family code. The next 8 bits are an external address byte, of which the lower 7 bits are connected to the address input pins ...
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... X MEMORY The DS28E04-100 EEPROM array consists of 17 pages of 32 bytes each, starting at address 0000h and ending at address 021Fh. All memory addresses in this range have unrestricted read access. The data memory consists of 16 pages of 32 bytes each. The register page consists of 32 bytes starting at address 0200h. It contains 16 page protection control bytes (one for each data memory page), the register page lock byte, the factory bytes, and the reserved bytes ...
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Figure 5. Memory Map Address locations 0000h to 021Fh are nonvolatile. Address locations 0220h to 0225 are volatile. ADDRESS RANGE TYPE 0000h to 001Fh R/(W) 0020h to 003Fh R/(W) 0040h to 005Fh R/(W) 0060h to 007Fh R/(W) 0080h to 009Fh ...
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PIO-RELATED REGISTERS Figure 6 shows the simplified logic diagram of a PIO channel. The registers related to the PIO pins are located in the address range 0220h to 0225h. All these registers are volatile, i.e., they lose their state when ...
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PIO Activity Latch State Register ADDR b7 b6 0222h 0 0 The data in this register represents the current state of the PIO activity latches. This register is read using the Read Memory command. This register is read-only. Each bit ...
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Conditional Search Channel Polarity Selection Register ADDR b7 b6 0224h 0 0 The data in this register specifies the polarity of each selected PIO channel for the device to respond to the conditional search command. This register can only be ...
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... Only) WRITING WITH VERIFICATION To write data to the DS28E04-100 EEPROM sections, the scratchpad has to be used as intermediate storage. First the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. Under certain conditions (see Write Scratchpad command) the master will receive an inverted CRC16 of the command, address (actual address sent), and data (as sent by the master) at the end of the Write Scratchpad command sequence ...
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... PIO pins of the DS28E04-100. Examples on how to use these functions are included at the end of this document. The communication between master and DS28E04-100 takes place either at standard speed (default Overdrive peed (OD = 1). If not explicitly set into the Overdrive Mode, the DS28E04-100 powers up in standard speed. ...
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... EPROM mode. If write- protected, then the DS28E04 copies the data byte from the target address into the scratchpad EPROM mode, then the DS28E04 stores the bitwise logical AND of the transmitted byte and the data byte from the targeted address into the scratchpad. ...
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... Bus Master RX Data Byte from Scratchpad Offset Y Master TX Reset ? N N Scrpad. Offset = E4: Bus Master RX CRC16 of Command, Address, E/S Byte, Data Bytes as sent by the DS28E04 N Master TX Reset ? Figure Part See note in Write Scratchpad flow chart for additional details. From Figure 9 ...
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... N RX “1”s N Master Y * 1-Wire idle high 10ms for power Figure Part Copy- Protected ? DS28E04 copies Scratch- * pad Data to Address DS28E04 TX “0” Y Master TX Reset ? N DS28E04 TX “1” N Master TX Reset ? Y From Figure Part ...
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Figure 9-4. Memory/Control Function Flow Chart (continued ...
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Figure 9-5. Memory/Control Function Flow Chart (continued ...
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Figure 9-6. Memory/Control Function Flow Chart (continued ...
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... In contrast to reading the PIO logical state from address 0220h, this command reads the PIO logical status in an endless loop. After 32 bytes of PIO pin status the DS28E04-100 inserts an inverted CRC16 into the data stream, which allows the master to verify whether the data was received error-free. A PIO Access Read can be terminated at any time with a 1-Wire Reset ...
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... AAh. After the MS bit of the confirmation byte is transmitted, the DS28E04-100 samples the status of the PIO pins, as shown in Figure 10, and sends it to the master. Depending on the data the master can either continue writing more data to the PIO or issue a 1-Wire reset to end the command. ...
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... Overdrive of 142kbps. The slightly reduced rates for the DS28E04-100 are a result of additional recovery times, which in turn were driven by a 1-Wire physical interface enhancement to improve noise immunity. The value of the pullup resistor primarily depends on the network size and load conditions. The DS28E04-100 requires a pullup resistor of 2.2kΩ ...
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... All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS28E04-100 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ...
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... Match ROM had been issued, since all other devices will have dropped out of the search process and will be waiting for a reset pulse. The DS28E04-100 responds to the conditional search if the CSR signal is active. See the description of the registers at addresses 0223h to 0225h and Figure 7 for more details ...
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... To Memory Functions Flow Chart (Figure From Figure 14 Figure 14 ECh N Cond. Search Command CSR = 1? Y DS28E04 TX Bit 0 DS28E04 TX Bit 0 Master TX Bit 0 N Bit 0 Match DS28E04 TX Bit 1 DS28E04 TX Bit 1 Master TX Bit 1 N Bit 1 Match Bit 63 ...
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Figure 14-2. ROM Functions Flow Chart (continued Figure 14, 1 Part From Figure Part CCh N Skip ROM Command From Figure Part To Figure Part ...
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... The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at Overdrive speed allows the bus master to address a specific DS28E04-100 on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS28E04-100 that exactly matches the 64-bit ROM sequence responds to the subsequent Memory/Control Function command ...
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... Read/Write Time Slots Data communication with the DS28E04-100 takes place in time slots, which carry a single bit each. Write time slots transport data from bus master to slave. Read time slots transfer data from slave to master. Figure 16 illustrates the definitions of the write and read time slots. ...
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... During the t RL data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS28E04-100 does not hold the data line low at all, and the voltage starts rising as soon over. ...
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... CRC GENERATION With the DS28E04-100 there are two different types of CRCs. One CRC is an 8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the ROM and, if none of the address inputs is connected to GND, compare it to the value stored within the DS28E04-100 to determine whether the ROM data has been received error-free ...
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Figure 18. CRC-16 Hardware Description and Polynomial STAGE STAGE STAGE STAGE STAGE COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL—LEGEND SYMBOL RST 1-Wire Reset ...
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COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL—COLOR CODES Master to slave Slave to master WRITE SCRATCHPAD (CANNOT FAIL) RST PD Select WS READ SCRATCHPAD (CANNOT FAIL) RST PD Select RS COPY SCRATCHPAD 1-Wire POWERED (SUCCESS) RST PD Select CPS COPY SCRATCHPAD (INVALID ADDRESS ...
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PIO ACCESS READ (CANNOT FAIL) RST PD Select PIOR PIO ACCESS WRITE (SUCCESS) RST PD Select PIOW INVALID DATA BYTE PIO ACCESS WRITE ( RST PD Select PIOW PIO ACCESS PULSE (SUCCESS) RST PD Select PIOP INVALID SELECTION MASK PIO ...
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... MEMORY FUNCTION EXAMPLE Write 5 bytes to memory page 1, starting at address 0021h. Read the entire memory and the PIO-related registers. With only a single DS28E04-100 connected to the bus master, the communication looks like this: MASTER MODE ...
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... The inverted CRC16 is transmitted after 32 bytes of PIO data. PIO ACCESS WRITE EXAMPLE Set both PIOs to 0 and then to 1. Both PIOs are pulled high to V With only a single DS28E04-100 connected to the bus master, the communication looks like this: MASTER MODE TX RX ...
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... PIO ACCESS PULSE EXAMPLE Generate a pulse on PIO1. Both PIOs are pulled high to V With only a single DS28E04-100 connected to the bus master, the communication looks like this: MASTER MODE The "X" indicates the state of PIO0, which is not defined in this example. ...
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... Added Package Information section and Revision History. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...