DS1306 Maxim, DS1306 Datasheet
DS1306
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DS1306 Summary of contents
Page 1
... N.C. INT0 7 8 INT1 1Hz 9 10 GND TSSOP (4.4mm CC2 2 V BAT INT0 6 INT1 7 1Hz 8 GND DIP (300 mils DS1306 V 20 CC1 N.C. 19 32kHz CCIF SDO 16 SDI 15 14 SCLK 13 N. SERMODE 16 V CC1 15 32kHz 14 V CCIF 13 ...
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... X2 pin is floated. Active-Low Interrupt 0 Output. The INT0 pin is an active-low output of the DS1306 that can be used as an interrupt input to a processor. The INT0 pin can be programmed to be asserted by Alarm 0. The INT0 pin remains low as long as the status bit causing the interrupt is present and the corresponding interrupt enable bit is set ...
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... Output. The 32kHz pin provides a 32.768kHz output. This signal is always present. V provides the logic-high level. CCIF Primary Power Supply. DC power is provided to the device on this pin the primary power supply. CC1 No Connection (as long as a power CC , SPI CC provides the logic-high level. CCIF pin allows the DS1306 to CCIF ...
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... A 1Hz and a 32kHz clock output are also available. The DS1306 supports a direct interface to SPI serial data ports or standard 3-wire interface. An easy-to- use address and data format is implemented in which data transfers can occur 1 byte at a time or in multiple-byte burst mode ...
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RECOMMENDED LAYOUT FOR CRYSTAL Local ground plane (Layer 2) crystal CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and ...
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... Note: Range for alarm registers does not include mask’m’ bits. The DS1306 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic-high being PM ...
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... SPECIAL PURPOSE REGISTERS The DS1306 has three additional registers (control register, status register, and trickle charger register) that control the real-time clock, interrupts, and trickle charger. CONTROL REGISTER (READ 0Fh, WRITE 8Fh) BIT7 BIT6 (Write Protect) – Before any write operation to the clock or RAM, this bit must be logic 0. When high, the write protect bit prevents a write operation to any register, including bits 0, 1, and 2 of the control register ...
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... In order to prevent accidental enabling, only a pattern of 1010 enables the trickle charger. All other patterns disable the trickle charger. The DS1306 powers up with the trickle charger disabled. The diode select (DS) bits (bits 2–3) select whether one diode or two diodes are ...
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... DS1306. The DS1306 does not write-protect itself in this configuration. CC2 CC2 Configuration 3 shows the DS1306 in battery-operate mode, where the device is powered only by a single battery. In this case, the V CC1 Only these three configurations are allowed. Unused supply pins must be grounded. ...
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Figure 4. POWER-SUPPLY CONFIGURATIONS NOTE: DEVICE IS WRITE-PROTECTED IF V NOTE: DEVICE DOES NOT PROVIDE AUTOMATIC WRITE PROTECTION. CONFIGURATION 1: BACKUP SUPPLY IS NONRECHARGEABLE LITHIUM BATTERY < CCTP CONFIGURATION 2: BACKUP SUPPLY IS A RECHARGEABLE BATTERY OR ...
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... SCLK (serial clock). The DS1306 is the slave device in an SPI application, with the microcontroller being the master. The SDI and SDO pins are the serial data input and output pins for the DS1306, respectively. The CE input is used to initiate and terminate a data transfer. The SCLK pin is used to synchronize data movement between the master (microcontroller) and the slave (DS1306) devices ...
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... Data transfers can occur one byte at a time or in multiple-byte burst mode. After CE is driven high an address is written to the DS1306. After the address more data bytes can be written or read. For a single-byte transfer, one byte is read or written and then CE is driven low. For a multiple-byte transfer, however, multiple bytes can be read or written to the DS1306 after the address has been written ...
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Figure 8. SPI MULTIPLE-BYTE BURST TRANSFER READING AND WRITING IN BURST MODE Burst mode is similar to a single-byte read or write, except that CE is kept high and additional SCLK cycles are sent until the end of the burst. ...
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Figure 9. 3-WIRE SINGLE BYTE TRANSFER CE SCLK I/ SCLK I/ NOTE: IN BURST MODE KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST. *I/O IS SDI ...
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... Logic 1 Input Logic 0 Input V Battery Voltage BAT V Supply Voltage CCIF Specification V CC 2.0 to 5.5 V 2.0 to 5.5 V SYMBOL MIN , V 2.0 CC1 CC2 2.0 BAT V 2.0 CCIF ( CC1 CC2 or V CC1 CC2 TYP MAX UNITS 5 0 +0.3 V +0.8 5.5 V 5.5 V DS1306 NOTES ...
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DC ELECTRICAL CHARACTERISTICS (T = Over the operating range, unless otherwise specified.) A PARAMETER Input Leakage Output Leakage I = 1.5mA OL Logic 0 Output I = 4.0mA -0.4mA OH Logic 1 Output I = -1.0mA OH ...
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... CC t CCH 2. CWH 2. CDZ 2. CCZ DS1306 TYP MAX UNITS NOTES ns ns 800 200 ns ns 0.6 MHz 2.0 2000 ns 500 s ns s 280 ns 70 280 ...
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Figure 10. TIMING DIAGRAM: 3-WIRE READ DATA TRANSFER SERMODE = GND * I/O IS SDI AND SDO TIED TOGETHER. Figure 11. TIMING DIAGRAM: 3-WIRE WRITE DATA TRANSFER SERMODE = GND * I/O IS SDI AND SDO TIED TOGETHER ...
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... 2.0V 240 CC t CCH 2. CWH 2. CDZ TYP MAX UNITS NOTES ns ns 800 ns 200 ns ns 0.6 MHz 2.0 2000 ns 500 s ns s 280 ns 70 DS1306 ...
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Figure 12. TIMING DIAGRAM: SPI READ DATA TRANSFER SERMODE = SCLK CAN BE EITHER POLARITY, TIMING SHOWN FOR CPOL = 1. Figure 13. TIMING DIAGRAM: SPI WRITE DATA TRANSFER SERMODE = SCLK CAN BE ...
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... V < CC1 BAT 10) V must be less than or equal to the largest of V CCIF PACKAGE INFORMATION For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE 16 PDIP 20 TSSOP , SCLK = 2MHz 0.8V and 10ms maximum rise and fall time ...
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... © 2009 Maxim Integrated Products DESCRIPTION ” to Figures 6, 7, 12, and 13 Maxim Is a registered trademark of Maxim Integrated Products, Inc. DS1306 PAGES CHANGED 5 12 ...