DS1340 Maxim, DS1340 Datasheet
DS1340
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DS1340 Summary of contents
Page 1
... Rev 7; 8/11 General Description The DS1340 is a real-time clock (RTC)/calendar that is pin compatible and functionally equivalent to the ST M41T00, including the software clock calibration. The device additionally provides trickle-charge capability on the V pin, a lower timekeeping voltage, and BACKUP an oscillator STOP flag. Block access of the register map is identical to the ST device ...
Page 2
... OLSDA 1.7V < V < > 1.7V < V < OLSQW CC OL 1.3V < V < 1.7V 0. DS1340-18 1.89V CC I DS1340- 3.3V CCA CC DS1340-33 5.5V CC DS1340-18 1.89V CC I DS1340- 3.3V CCS CC DS1340-33 5. 3.7V BACKUP = 3.3V +25°C, unless CC A MIN TYP MAX 1.71 1.8 5.5 2 ...
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DC ELECTRICAL CHARACTERISTICS ( 3.7V -40°C to +85°C, unless otherwise noted.) (Note 1) CC BACKUP A PARAMETER SYMBOL I BACKUP1 I BACKUP2 V Current BACKUP I BACKUP3 V Data-Retention Current I BACKUP BACKUPDR AC ...
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... A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V signal) to bridge the undefined region of the falling edge of SCL. Note 13: The maximum t only has to be met if the device does not stretch the low period (t HD:DAT ...
Page 5
PF(MAX) V PF(MIN) INPUTS RECOGNIZED OUTPUTS VALID Figure 2. Power-Up/Power-Down Timing (V = +3.3V +25°C, unless otherwise noted vs CCSA CC 250 200 150 100 50 0 1.0 ...
Page 6
... N.C. No Connection. Must be connected to ground. Detailed Description The DS1340 is a low-power clock/calendar with a trickle charger. Address and data are transferred serially 2 through bidirectional bus. The clock/calendar pro- vides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year ...
Page 7
... Typical accuracy with nominal V and +25°C is approximately +15ppm. Refer to Application Note 58 for information about crystal accu- racy vs. temperature. The DS1340 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code fol- lowed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed ...
Page 8
... SCL SDA Figure 5. Functional Diagram Address Map Table 3 shows the DS1340 address map. The RTC reg- isters are located in address locations 00h to 06h, and the control register is located at 07h. The trickle-charge and flag registers are located in address locations 08h to 09h. During a multibyte access of the timekeeping registers, when the address pointer reaches 07h— ...
Page 9
... This eliminates the need to reread the registers in case the internal regis- ters update during a read. The divider chain is reset whenever the seconds regis- ter is written. Write transfers occur on the acknowledge from the DS1340. Once the divider chain is reset, to BIT 7 BIT 6 BIT 5 TCS3 ...
Page 10
... Attempting to write OSF to logic 1 leaves the value unchanged. Bits All other bits in the flag register read as 0 and cannot be written. . Also BACKUP The DS1340 provides a digital clock calibration feature and allow compensation for crystal and temperature vari- CC BACKUP ations ...
Page 11
... The devices that are con- trolled by the master are slaves. A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP condi- tions must control the bus. The DS1340 operates as a MSB FIRST SDA SLAVE ...
Page 12
... START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. The DS1340 can operate in the following two modes: Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. ...
Page 13
ADDRESS> <R/W> <WORD ADDRESS (n)> S 1101000 0 A XXXXXXXX S - START MASTER TO SLAVE A - ACKNOWLEDGE (ACK STOP R/W - READ/WRITE OR DIRECTION BIT ADDRESS Figure 8. Data Write—Slave Receiver Mode <SLAVE ADDRESS> <R/W> ...
Page 14
... I C RTC with Trickle Charger Handling, PC Board Layout, and Assembly The DS1340C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. Exposure to reflow is limited to 2 times maximum. Ultrasonic cleaning should be avoided to prevent damage to the crystal ...
Page 15
... In Table 1, added increased crystal ESR with increased supply minimum voltage requirement. 2 12/04 Added the DS1340C Only section. Updated Figure 5 to also show the “C Version” crystal. Added the Handling, PC Board Layout, and Assembly section. Added the integrated-crystal package Theta-JA and Theta-JC information to the Thermal Information section ...
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... EC tables and notes Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...