DS80C310 Maxim, DS80C310 Datasheet
DS80C310
Available stocks
Related parts for DS80C310
DS80C310 Summary of contents
Page 1
... The DS80C310 offers a 25MHz maximum crystal speed, resulting in apparent execution speeds of 62.5MHz (approximately 2.5x). The DS80C310 is pin compatible with the standard 80C32 and includes standard resources such as three timer/counters, 256 bytes of RAM, and a serial port. It also provides dual data pointers (DPTRs) to speed block data memory moves ...
Page 2
... ORDERING INFORMATION PART DS80C310-MCG DS80C310-MCG+ DS80C310-QCG DS80C310-QCG+ DS80C310-QNG DS80C310-QNG+ DS80C310-ECG DS80C310-ECG+ Denotes a lead(Pb)-free/RoHS-compliant device. + Figure 1. Block Diagram MAX CLOCK TEMP RANGE SPEED (MHz) 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C 0 ...
Page 3
... When software writes any port pin, the DS80C310 activates a strong pulldown that remains on until either written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup ...
Page 4
... GND Digital Circuit Ground Address Outputs (Port 2) (Output). Port 2 serves as the MSB for external addressing. P2.7 is A15 and P2.0 is A8. The DS80C310 automatically places the MSB of an address on P2 for external ROM and RAM access. Although Port 2 can be accessed like an ordinary I/O port, the value stored on the Port 2 latch is never seen on the pins (due to memory access) ...
Page 5
... COMPATIBILITY The DS80C310 is a fully static, CMOS, 8051-compatible microcontroller designed for high performance. In most cases the DS80C310 can drop into an existing socket for the 80C31 or 80C32 to significantly improve the operation. In general, software written for existing 8051-based systems works without modification on the DS80C310. The exception is critical timing because the high-speed microcontroller performs its instructions much faster than the original for any given crystal selection ...
Page 6
... Therefore, they required the same amount of time. In the DS80C310, the MOVX instruction takes as little as 2 machine cycles or 8 oscillator cycles but the “MOV direct, direct” uses 3 machine cycles or 12 oscillator cycles. While both are faster than their original counterparts, they now have different execution times ...
Page 7
... SPECIAL FUNCTION REGISTERS (SFRs) Special Function Registers control most special features of the DS80C310. The High-Speed Microcontroller User’s Guide contains descriptions of all the SFRs. Functions that are not part of the standard 80C32 are in bold. Table 1. Special Function Registers REGISTER BIT 7 BIT 6 SP — ...
Page 8
... MEMORY ACCESS The DS80C310 has 256 bytes of scratchpad RAM, but contains no on-chip ROM. Off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2. Timing diagrams are provided in the Absolute Maximum Ratings section. Program memory (ROM) is accessed at a fixed rate determined by the crystal frequency and the actual instructions ...
Page 9
... DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the DS80C310, the standard data pointer is called DPTR and is located at SFR addresses 82h and 83h. These are the standard locations. No modification of standard code is needed to use DPTR. The new DPTR is located at SFR 84h and 85h and is called DPTR1 ...
Page 10
... CKCON bit is logic 1, the DS80C310 uses 4 clocks per cycle to generate timer speeds. When the bit is 0, the DS80C310 uses 12 clocks for timer speeds. The reset condition is 0. CKCON.5 selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer 0. Note that unless a user desires very fast timing unnecessary to alter these bits ...
Page 11
... IH2 V 0.15 OL1 V 0.15 OL2 V 2.4 OH1 V 2.4 OH2 V 2.4 OH3 -300 RST = RST = 5.5V, all other pins disconnected 5.5V, RST at ground, all other pins CC =5.5V, all other pins disconnected DS80C310 + 0.5V) CC MAX UNITS NOTES 5 0.3 0. ...
Page 12
... Note 10: 2V. Note 11: 0.45 < V <V . Not a high-impedance input. This port is a weak address holding latch because Port 0 is dedicated address bus on the DS80C310. Peak current occurs near the input transition point of the latch, approximately 2V. Figure 2. Typical I vs. Frequency DS80C310 ...
Page 13
... AVLL t 2 (Note 2) LLAX1 t 56 LLIV t 7 LLPL t 55 PLPH t 41 PLIV t 0 PXIX t 26 PXIZ t 71 AVIV1 t 81 AVIV2 t (Note 2) PLAZ DS80C310 VARIABLE CLOCK UNITS MIN MAX 0 25 MHz 1 25 1.5t - CLCL ns 5 0.5t - CLCL ns 5 0.5t - CLCL (Note 2.5t - CLCL ns 20 0.5t ...
Page 14
... CLCL 4 machine cycles 8 t CLCL 5 machine cycles 12 t CLCL 6 machine cycles 16 t CLCL 7 machine cycles 20 t CLCL 8 machine cycles 24 t CLCL 9 machine cycles 28 t CLCL DS80C310 STRETCH UNITS (Note 1) MAX t MCS ns t MCS t MCS ns t MCS t MCS ns t MCS t ...
Page 15
... SM2 = 0, 12 clocks per cycle XHQX SM2 = 1, 4 clocks per cycle SM2 = 0, 12 clocks per cycle XHDX SM2 = 1, 4 clocks per cycle SM2 = 0, 12 clocks per cycle XHDV SM2 = 1, 4 clocks per cycle DS80C310 TYP MAX UNITS ...
Page 16
... EXTERNAL PROGRAM MEMORY READ CYCLE DS80C310 ...
Page 17
... EXTERNAL DATA MEMORY READ CYCLE DS80C310 ...
Page 18
... DATA MEMORY WRITE CYCLE DATA MEMORY WRITE WITH STRETCH = DS80C310 ...
Page 19
... DATA MEMORY WRITE WITH STRETCH = 2 EXTERNAL CLOCK DRIVE DS80C310 ...
Page 20
... SERIAL PORT MODE 0 TIMING DS80C310 ...
Page 21
... PACKAGE INFORMATION For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE 44 TQFP 40 PDIP 44 PLCC PACKAGE CODE C44+2 P40+1 Q44 DS80C310 DOCUMENT NO. 21-0293 21-0044 21-0049 ...
Page 22
... © 2009 Maxim Integrated Products DESCRIPTION specification. IL specification Maxim is a registered trademark of Maxim Integrated Products, Inc. DS80C310 PAGES CHANGED to QVXL 13 ...