DS89C440 Maxim, DS89C440 Datasheet
DS89C440
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DS89C440 Summary of contents
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... MIPS performance from a maximum 33MHz clock rate. The DS89C440 is a 32kB version of the DS89C450 that is no longer available. The DS89C450 can be used as a drop-in replacement. The Ultra-High-Speed Flash Microcontroller User’s Guide should be used in conjunction with this data sheet ...
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... Soldering Temperature…………………………………………………………………………………………See IPC/JEDEC J-STD-020 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied ...
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... When addressing external memory. Note 11: Guaranteed by design. Note 12: Ports 1, 2, and 3 source transition current when pulled down externally. The current reaches its maximum at approximately 2V. Note 13: RST = 5.5V. Port 0 is floating during reset and when in the logic-high state during I/O mode. Note 14: This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latch at approximately 2V ...
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AC CHARACTERISTICS (V = 4.5V to 5.5V -40°C to +85°C.) (See CC O PAGE MODE 1 PARAMETER SYMBOL MIN System Clock External 1/t CLCL Oscillator (Note 15) System Clock External Crystal 1/t CLCL (Note 15) 0.5t CLCL ALE ...
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AC CHARACTERISTICS (continued 4.5V to 5.5V -40°C to +85°C.) (See CC O PAGE MODE 1 PARAMETER SYMBOL MIN PSEN Low to Valid Instruction t PLIV In Input Instruction Hold After t PXIX PSEN Input Instruction Float ...
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AC CHARACTERISTICS (continued 4.5V to 5.5V -40°C to +85°C.) (See CC O PAGE MODE 1 PARAMETER SYMBOL MIN Port 0 Address to Valid Data t AVDV0 In (Note 16) Port 2 Address to Valid Data t ...
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... Note 17: Maximum load capacitance (to meet the above timing) for Port 0, ALE, PSEN, WR, and RD is limited to 60pF. XTAL1 and XTAL2 load capacitance are dependent upon the frequency of the selected crystal. Figure 1. Nonpage Mode Timing XTAL1 t CLCL ALE t AVLL2 ...
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Figure 2. Page Mode 1 Timing XTAL1 t CLCL ALE t AVLL2 PSEN AVIV2 Port 0 MOVX OPCODE LSB LSB LSB Port 2 Figure 3. Page Mode 2 Timing XTAL1 t CLCL ALE t AVLL t AVLL2 ...
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EXTERNAL CLOCK CHARACTERISTICS (V = 4.5V to 5.5V -40°C to +85°C PARAMETER Clock High Time Clock Low Time Clock Rise Time Clock Fall Time SERIAL PORT MODE 0 TIMING CHARACTERISTICS (V = 4.5V to 5.5V, T ...
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Figure 4. Serial Port Timing SERIAL PORT (SYNCHRONOUS MODE) SM2 = 1 TDX CLOCK = XTAL FREQ/4 ALE PSEN t QVXH WRITE TO SBUF RXD DATA OUT TXD CLOCK TI WRITE TO SCON TO CLEAR RI RXD DATA IN TXD ...
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POWER-CYCLE TIMING CHARACTERISTICS (V = 4.5V to 5.5V -40°C to +85°C PARAMETER Crystal Startup Time (Note 18) Power-On Reset Delay (Note 19) Note 18: Startup time for a crystal varies with load capacitance and manufacturer. The ...
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PIN DESCRIPTION PIN PDIP PLCC TQFP 40 12 22, 23, 16, 17, 28 ALE/PROG P0.0 ...
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PIN DESCRIPTION (continued) PIN PDIP PLCC TQFP P2.0 (A8 P2.1 ...
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Figure 5. Functional Diagram CONTROL AND SEQUENCER DECODER IR INTERNAL CONTROL BUS SERIAL I/O WATCHDOG TIMER AND POWER MANAGER Dallas Semiconductor DS89C430/ DS89C450 DETAILED DESCRIPTION The DS89C430 and DS89C450 are pin compatible with all three packages of the standard 8051 ...
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Terminology The term DS89C430 is used in the remainder of the document to refer to the DS89C430 and DS89C450, unless otherwise specified. Compatibility The DS89C430 is a fully static CMOS 8051-compatible microcontroller similar in functional features to the DS87C520, but ...
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All standard SFR locations from the 8051 are duplicated in the DS89C430, and several SFRs have been added for the unique features of the DS89C430. Most of these features are controlled by bits in SFRs located in unused locations in ...
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Table 1. SFR Register Map (continued) REGISTER ADDRESS BIT 7 TH1 8Dh CKCON 8Eh WD1 P1 90h P1.7/INT5 EXIF 91h IE5 CKMOD 96h SCON0 98h SM0/FE_0 SBUF0 99h ACON 9Dh PAGEE P2 A0h P2.7 IE A8h EA SADDR0 A9h SADDR1 ...
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Table 2. SFR Reset Value REGISTER ADDRESS P0 80h SP 81h DPL 82h DPH 83h DPL1 84h DPH1 85h DPS 86h PCON 87h TCON 88h TMOD 89h TL0 8Ah TL1 8Bh TH0 8Ch TH1 8Dh CKCON 8Eh P1 90h EXIF ...
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... The program and data segments can be overlapped since they are accessed in different manners. If the maximum address of on-chip program or data memory is exceeded, the DS89C430 performs an external memory access using the expanded memory bus. The PSEN signal goes active low to serve as a chip enable or output enable when performing a code fetch from external program memory ...
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... SRAM for on-chip data memory or a particular range (400–7FF) of “alternate” program memory space. The DS89C450 incorporates two 32kB flash memories. The DS89C430 uses an address scheme that separates program memory from data memory such that the 16-bit address bus can address each memory area up to maximum of 64kB. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers FFFF ...
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... The reset default condition for all devices is to their maximum on-chip program memory size. When accessing external program memory, that amount of external memory would be inaccessible. To select a smaller effective program memory size, software must alter bits RMS2–RMS0. Altering these bits requires a timed-access procedure, as explained later ...
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Page mode 1 is the only external addressing mode where the CPU does not require stalls for external memory access, but page misses result in reduced external access performance. On-Chip Program Memory The processor can ...
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... The flash command (FC3–FC0;FCNTL.3:0) bits provide flash commands as listed in DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers MEANING Manufacturer ID DS89C430 Device ID DS89C440 Device ID (Contact factory or replace with DS89C430 or DS89C450.) DS89C450 Device ID Device Extension rite upper program memory bank " is shown below. The command must be Table 4 ...
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Table 4. In-Application Programming Commands FC3:FC0 COMMAND 0000 Read Mode 0001 Verify Option Control Register 0010 Verify Security Block Verify Upper Program 0011 Memory Bank 0100 Reserved for Future Use 1000 Reserved for Future Use 1001 Write Option Control Register ...
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... MOVC A, @A+DPTR MOVX A, @DPTR MOVX @DPTR, A Windows is a registered trademark of Microsoft Corporation. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers ID0 SEL = 0 SEL = 1 0 INC DPTR INC DPTR1 1 DEC DPTR INC DPTR1 0 INC DPTR DEC DPTR1 1 DEC DPTR DEC DPTR1 www.maxim-ic.com/support for more ...
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External Memory The DS89C430 executes external memory cycles for code fetches and read/writes of external program and data memory. A nonpage external memory cycle is four times slower than the internal memory cycles (i.e., an external memory cycle contains four ...
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External Data Memory Interface in Nonpage Mode Operation Just like the program memory cycle, the external data memory cycle is four times slower than the internal data memory cycle in nonpage mode. A basic internal memory cycle contains one system ...
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Figure 8. Nonpage Mode, External Data Memory Access (Stretch = 0, CD1:CD2 = 10) XTAL1 ALE PSEN RD/WR Port 0 A MOVX Port 2 A MOVX Instruction Fetch Figure 9. Nonpage Mode, External Data Memory Access (Stretch = 1, CD1:CD2 ...
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Page Mode, External Memory Cycle Page mode retains the basic circuitry requirement for an original 8051 external memory interface, but alters the configuration of P0 and P2 for the purposes of address output and data I/O during external memory cycles. ...
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Figure 10. Page Mode 1, External Memory Cycle (CD1:CD0 = 10) Internal Memory Cycles XTAL1 ALE PSEN RD/WR Port 0 Port 2 MSB LSB Page Miss ALE PSEN RD/WR Port 0 Port 2 MSBAdd ALE PSEN RD/WR Port 0 Port ...
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Note that there are a few exceptions for this mode of operation when PAGES1 and PAGES2 are set to 00b: PSEN is asserted for both a page hit and a page miss for a full clock cycle. The ...
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Table 7. Page Mode 1, Data Memory Cycle Stretch Values (PAGES1:PAGES0 = 00) STRETCH 4X CD1, MD2:MD0 CYCLES 000 0 001 1 010 2 011 3 100 7 101 8 110 9 111 10 Table 8. Page Mode ...
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Table 10. Page Mode 2, Data Memory Cycle Stretch Values (PAGES1:PAGES0 = 11) STRETCH MD2:MD0 4X CD1, CYCLES 000 0 001 1 010 2 011 3 100 7 101 8 110 9 111 10 As shown in the ...
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Figure 12. Page Mode 1, External Data Memory Access (PAGES = 01, STRETCH = 10) XTAL1 ALE PSEN Inst Inst Port 0 LSB Addr LSB Addr Port 2 ALE PSEN Inst ...
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Figure 13. Page Mode 1, External Data Memory Access (PAGES = 01, Stretch = 10) Cycle XTAL1 ALE PSEN RD/WR Inst Inst Inst Port 0 Port 2 LSB LSB LSB MOVX Instruction Fetch Cycle ALE PSEN RD/WR ...
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Interrupt Priority There are five levels of interrupt priority: Level The highest interrupt priority is level 4, which is reserved for the power-fail interrupt. All other interrupts have individual priority bits in the interrupt priority registers to ...
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Timer/Counters The DS89C430 incorporates three 16-bit timers. All three timers can be used as either counters of external events, where 1-to-0 transitions on a port pin are monitored and counted, or timers that count oscillator cycles. summarizes the timer functions. ...
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... When using the clock multiplier feature, the external clock source frequency, multiplied by the clock multiplier (2X or 4X) can never be faster than the maximum rated speed of the device. Thus designer wished to use the 4X clock multiplier on a device rated at 33MHz, the maximum external clock speed would be 8.25MHz. ...
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Figure 14. System Clock Sources CRYSTAL OSCILLATOR RING ENABLE Bandgap-Monitored Interrupt and Reset Generation The power monitor in the DS89C430 monitors the V Whenever V falls below interrupt is generated if the corresponding power-fail interrupt-enable bit EPFI ...
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Watchdog Timer The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. When the clock divider is set to 10b, the interrupt timeout has a default divide ratio of 2 watchdog reset set to ...
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... If a flash write or erase operation was in progress, the reset state is a 4ms maximum flash write or erase operations were in progress, there is a delay of 90 external clock cycles. Operation resumes at address 0000h. If taking RST to a logic low causes the device to exit stop mode, an additional delay of 65,536 clock cycles is experienced before operation begins ...
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Serial ports and timers track the oscillator cycles per machine cycle when the higher divide ratio of 1024 is selected, and require the switchback function to automatically return to the divide-by-1 mode for proper operation when a qualified event occurs. ...
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Stop Mode Stop mode disables all circuits within the processor. All on-chip clocks, timers, and serial port communication are stopped, and no processing is possible. Stop mode is invoked by setting the stop bit (PCON.1) to logic 1. The processor ...
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... DS89C430-MNG+ -40°C to +85°C DS89C430-QNG -40°C to +85°C DS89C430-QNG+ -40°C to +85°C DS89C430-ENG -40°C to +85°C DS89C430-ENG+ -40°C to +85°C DS89C440-xxx DS89C450-MNL -40°C to +85°C DS89C450-MNL+ -40°C to +85°C DS89C450-QNL -40°C to +85°C DS89C450-QNL+ -40°C to +85°C DS89C450-ENL -40°C to +85°C DS89C450-ENL+ -40° ...
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... DS89C430 DS89C450 17 18 PLCC 33 34 DS89C430 DS89C450 44 1 TQFP PACKAGE INFORMATION For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE 44 TQFP C44+2 40 PDIP P40+3 40 PLCC Q44+7 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers 40 39 P1.0/T2 P1.1/T2EX P1.2/RXD1 P1 ...
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... Clarified IAP programming sequence. 060805 Added lead-free devices to Ordering Information table. Removed references to DS89C440 and/or added “Contact factory or replace with DS89C430 or 091906 DS89C450.” Added clarification to the Security Features section and Table 3 that flash security levels 1, 2, and 3 040507 should not be used when executing external code (page 22) ...