73S1217F Maxim, 73S1217F Datasheet
73S1217F
Related parts for 73S1217F
73S1217F Summary of contents
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... Teridian 73S1217F suitable for both development and production phases. Teridian Semiconductor Corporation offers with its 73S1217F a very comprehensive set of software libraries, including the smart card and USB protocol layers that are pre-approved against USB, Microsoft WHQL and EMV, as well as a CCID reference design. Refer to the Teridian Semiconductor Corporation 73S12xxF Software User’ ...
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FEATURES 80515 Core: • 1 clock cycle per instruction (most instructions) • CPU clocked up to 24MHz • 64kB Flash memory (lockable) • 2kB XRAM (User Data Memory) • 256 byte IRAM • Hardware watchdog timer Oscillators: • Single low-cost ...
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... Application Schematics ................................................................................................................. 114 2.1 Typical Application Schematic 1 ............................................................................................... 114 2.2 Typical Application Schematic 2 ............................................................................................... 115 3 Electrical Specification ................................................................................................................... 116 3.1 Absolute Maximum Ratings ...................................................................................................... 116 3.2 Recommended Operating Conditions ...................................................................................... 116 3.3 Digital IO Characteristics .......................................................................................................... 117 3.4 Oscillator Interface Requirements ............................................................................................ 118 3.5 DC Characteristics: Analog Input ............................................................................................. 118 ...
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... Figure 25: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode ................................. 87 Figure 26: Operation of 9-bit Mode in Sync Mode ...................................................................................... 88 Figure 27: 73S1217F Typical Application Schematic (Handheld USB PINpad, with Combo USB- Bus and Self-powered Configuration) ..................................................................................... 114 Figure 28: 73S1217F Typical Application Schematic (USB Transparent Reader and USB Key Configuration) ...
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Tables Table 1: 73S1217 Pinout Description ........................................................................................................... 8 Table 2: MPU Data Memory Map ............................................................................................................... 11 Table 3: Flash Special Function Registers ................................................................................................. 13 Table 4: Internal Data Memory Map ........................................................................................................... 14 Table 5: Program Security Registers .......................................................................................................... 17 Table ...
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Table 58: The INT5Ctl Register .................................................................................................................. 56 Table 59: The ACOMP Register ................................................................................................................. 57 Table 60: The INT6Ctl Register .................................................................................................................. 58 Table 61: The LEDCtl Register ................................................................................................................... 59 Table 62: The DAR Register ....................................................................................................................... 63 Table 63: The WDR Register ...
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VDD PLL and TIMEBASES X12IN 12MHz OSCILLATOR X12OUT X32IN 32kHz OSCILLATOR X32OUT RTC VDD USB I/O D+ and D- LOGIC GND ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 KEYPAD INTERFACE COL0 COL1 COL2 COL3 COL4 USR0 USR1 USR2 USR3 USR4 USR5 ...
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Hardware Description 1.1 Pin Description Pin Name X12IN 10 I Figure 29 X12OUT 11 O Figure 29 X32IN 8 I Figure 30 X32OUT 7 O Figure Figure Figure 45 ROW(5:0) 0 ...
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... Power control pin. Connected to normally open SPST switch to ground. Closing switch for duration greater than de- bounce period will turn 73S1217F on. If 73S1217F is on, closing switch will flag the 73S1217F the off state. Firmware will control when the power is shut down. 9 ...
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... Reset input, positive assertion. Resets logic and registers to default condition. Note: to insure proper reset operation after V is turned on by application the ON/OFF switch, external reset circuitry must generate a proper reset signal to the 73S1217F. This can be accomplished via a simple RC network. section. power or activation of BUS Rev. 1.2 ...
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... Hardware Overview The 73S1217F single smart card controller integrates all primary functional blocks required to implement a smart card reader with host serial and / or USB interface. Included on chip are an 8051-compatible microprocessor (MPU) which executes up to one instruction per clock cycle (80515), a fully integrated IS0 7816 compliant smart card interface, expansion smart card interface, full speed USB 2 ...
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... Flash and XRAM writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL = 1. Table 3 shows the location and description of the 73S1217F flash-specific SFRs. Any flash modifications must set the CPUCLK to operate at 3.6923 MHz before any flash memory operations are executed to insure the proper timing when modifying the flash memory ...
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Table 3: Flash Special Function Registers Register SFR R/W Address ERASE 0x94 W PGADDR 0xB7 R/W FLSHCTL 0xB2 R/W W R/W Internal Data Memory: The internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data ...
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Addres Direct Addressing s 0xFF 0x80 0x7F 0x30 0x2F 0x20 0x1F 0x00 External Data Memory: While the 80515 can address up to 64KB of external data memory in the space from 0x0000 to 0xFFFF, only the memory ranges shown in ...
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Address Use Address 0xFFFF 0xFFFF 0XFF80 0xFF7F 0XFE00 0xFDFF 0XFC00 0xFBFF 0x0800 0x07FF Flash Program Memory 64K Bytes 0x0000 0x0000 Program Memory External Data Memory Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard ...
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Program Security Two levels of program and data security are available. Each level requires a specific fuse to be blown in order to enable or set the specific security mode. Mode 0 security is enabled by setting the SECURE ...
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Register SFR R/W Address FLSHCTL 0xB2 R/W W R/W TRIMPCtl 0xFFD1 W FUSECtl 0xFFD2 W SECReg 0xFFD7 W R R/W R/W Rev. 1.2 Table 5: Program Security Registers Description Bit 0 (FLSH_PWE): Program Write Enable: 0 – MOVX commands refer ...
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... SP Only a few addresses are used, the others are not implemented. SFRs specific to the 73S1217F are shown in bold print (gray background). Any read access to unimplemented addresses will return undefined data, while most write access will have no effect. However, a few locations are reserved and not user configurable in the 73S1217F ...
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IRAM Special Function Registers (Generic 80515 SFRs) Table 7 shows the location of the SFRs and the value they assume at reset or power-up. Table 7: IRAM Special Function Registers Reset Values Name Location Reset Value SP 0x81 0x07 ...
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Name Location Reset Value KROW 0XD2 0x3F KSCAN 0XD3 0x00 KSTAT 0XD4 0x00 KSIZE 0XD5 0x00 KORDERL 0XD6 0x00 KORDERH 0XD7 0x00 BRCON 0xD8 0x00 A 0xE0 0x00 B 0xF0 0x00 1.5.3 External Data Special Function Registers (SFRs) A map ...
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Name Location Reset Value FUSECtl 0x FFD2 0x00 VDDFCtl 0x FFD4 0x00 SECReg 0x FFD7 0x00 MISCtl0 0x FFF1 0x00 MISCtl1 0x FFF2 0x10 LEDCtl 0x FFF3 0xFF Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the ...
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Program Status Word (PSW): MSB CV AC Bit Symbol PSW.7 CV Carry flag. PSW.6 AC Auxiliary Carry flag for BCD operations. PSW.5 F0 General purpose Flag 0 available for user. PSW.4 RS1 Register bank select control bits. The contents of ...
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... Oscillator and Clock Generation Oscillator and Clock Generation The 73S1217F has two oscillator circuits; one for the main CPU clock and another for the RTC. The The 73S1217F has two oscillator circuits; one for the main CPU clock and another for the RTC. The main oscillator circuit is designed to operate with various crystal or external clock frequencies ...
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The master clock control register enables different sections of the clock circuitry and specifies the value of the VCO Mcount divider. The MCLK must be configured to operate at 96MHz to ensure proper operation of some of the peripheral blocks ...
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... The CPU clock is available as an output on pin CPUCLK. 1MΩ 12MHz 22pF Note: The crystals should be placed as close as possible to the IC, and vias should be avoided. Rev. 1.2 0x0C Table 13: The MPUCKCtl Register MDIV.5 MDIV.4 MDIV.3 MDIV.2 MDIV.1 MDIV.0 Function 73S1217F 22pF 22pF Figure 4: Oscillator Circuit LSB 32KHz 22pF 25 ...
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... BAT ON_OFF Debounce Circuit INT MPU PWRDN* *PWRDN bit in MISCtl0 Figure 5: Detailed Power Management Logic Block Diagram The 73S1217F contains a power supply and converter circuit that takes power from any one of three sources BAT BUS V is specified to range from 2.7 to 6.5 volts. It can typically be supplied by a single cell battery with a PC voltage range of 2 ...
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... When placed into the “OFF” state, the 73S1217F will consume minimum current from V and V will be unavailable ( When in “ON” mode, the 73S1217F will operate normally, with all the features described in this document available. V and V will be available ( Whenever V power is supplied, the circuit will be automatically in the “ ...
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... PWRDN bit will shut down the converter and VP will turn off. This in turn will turn off the VDD supply and the 73S1217F will be turned “OFF”. The power down modes should only be initiated by setting the PWRDN bit in the individual control bits in various registers ...
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... INT0 and the program can resume. Figure 7 shows the detailed logic for waking up the 73S1217F from a power down state using these specific interrupt sources. Figure 8 shows the timing associated with the power down mode. ...
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USR0 USR1 USR[7:0] Control USR2 USR3 USR4 USRxINTSrc set to 4(ext INT0 high) USR5 or USR6 6(ext INT0 low) USR7 INT4 INT5 RESETB Notes: 1. The counters are clocked by the MPUCLK Terminal count (high at overflow) ...
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External Interrupt Control Register (INT5Ctl): 0xFF94 MSB PDMUX – RTCIEN RTCINT USBIEN Bit Symbol When set = 1, enables interrupts from USB, RTC, Keypad (normally going to int5), Smart Card interrupts (normally going to int4), or USR(7:0) pins (int0) to ...
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Miscellaneous Control Register 1 (MISCtl1): 0xFFF2 MSB – – Bit Symbol MISCtl1.7 – MISCtl1.6 – Flash Read Pulse enable (low). If FRPEN = 1, the Flash Read signal is passed through with no change. When FRPEN = 0 a one-shot ...
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Master Clock Control Register (MCLKCtl): 0x8F MSB HSOEN KBEN Bit Symbol High-speed oscillator enable. When set = 1, disables the high-speed crystal oscillator and VCO/PLL system. This bit is not changed when the MCLKCtl.7 HSOEN PWRDN bit is set but ...
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Power Control Register 0 (PCON): 0x87 The SMOD bit used for the baud rate generator is setup via this register. MSB SMOD – Bit Symbol PCON.7 SMOD If SM0D = 1, the baud rate is doubled. PCON.6 – PCON.5 – ...
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... These will be described in more detail in the respective sections. External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 73S1217F, for example the USB interface, USR I/O, RTC, smart card interface, analog comparators, etc. The external interrupt configuration is shown in Figure 9. ...
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Interrupt Overview When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 32. Once the interrupt service has begun, it can only be interrupted by a higher priority interrupt. The interrupt service is ...
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Interrupt Enable 1 Register (IEN1): 0xB8 MSB – SWDT Bit Symbol IEN1.7 – IEN1.6 SWDT Not used for interrupt control. IEN1.5 EX6 EX6 = 0 – disable external interrupt 6. IEN1.4 EX5 EX5 = 0 – disable external interrupt 5. ...
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Timer/Counter Control Register (TCON): 0x88 MSB TF1 TR1 Bit Symbol TCON.7 TF1 Timer 1 overflow flag. TCON.6 TR1 Not used for interrupt control. TCON.5 TF0 Timer 0 overflow flag. TCON.4 TR0 Not used for interrupt control. TCON.3 IE1 Interrupt 1 ...
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Interrupt Request Register (IRCON): 0xC0 MSB – – Bit Symbol IRCON.7 – IRCON.6 – IRCON.5 IEX6 External interrupt 6 flag. IRCON.4 IEX5 External interrupt 5 flag. IRCON.3 IEX4 External interrupt 4 flag. IRCON.2 IEX3 External interrupt 3 flag. IRCON.1 IEX2 ...
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... Enable external interrupt 5 EX6 Enable external interrupt 6 1.7.5.4 Power Down Interrupt Logic The 73S1217F contains special interrupt logic to allow INT0 to wake up the CPU from a power down (CPU STOP) state. See the Power Control Modes 1.7.5.5 Interrupt Priority Level Structure All interrupt sources are combined in groups, as shown in Table 27. ...
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Interrupt Priority 1 Register (IP1): 0xB9 MSB – – 1.7.5.6 Interrupt Sources and Vectors Table 32 shows the interrupts with their associated flags and vector addresses. Interrupt Request Flag Description N/A IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 ...
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... UART The 80515 core of the 73S1217F includes two separate UARTs that can be programmed to communicate with a host. The 73S1217F can only connect one UART at a time since there is only one set of TX and Rx pins. The MISCtl0 register is used to select which UART is connected to the TX and RX pins. Each UART has a different set of operating modes that the user can select according to their needs ...
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Power Control Register 0 (PCON): 0x87 The SMOD bit used for the baud rate generator is set up via this register. MSB SMOD – Bit Symbol PCON.7 SMOD PCON.6 – PCON.5 – PCON.4 – PCON.3 GF1 PCON.2 GF0 PCON.1 STOP ...
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... Serial Interface 0 Control Register (S0CON): 0x9B 44 0x00 Table 37: The MISCtl0 Register – – – Function This bit places the 73S1217F into a power down state UART loop back testing mode. The pins TXD and RXD are to be connected together externally (with SLPBK =1) and therefore: SLPBK SSEL Mode 0 0 ...
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Transmit and receive data are transferred via this register. MSB SM0 SM1 Bit Symbol S0CON.7 SM0 Mode S0CON.6 SM1 S0CON.5 SM20 Enables the inter-processor communication feature. S0CON.4 REN0 If set, enables serial reception. Cleared by software to disable reception. S0CON.3 ...
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Serial Interface Control Register (S1CON): 0x9B The function of the serial port depends on the setting of the Serial Port Control Register S1CON. MSB SM – Bit Symbol S1CON.7 SM S1CON.6 – S1CON.5 SM21 S1CON.4 REN1 S1CON.3 TB81 S1CON.2 RB81 ...
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... (T0 and T1 are the timer gating inputs derived from USR[0:7] pins, see the Ports section). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure proper recognition state, an input should be stable for at least 1 machine cycle. ...
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Table 41: Timers/Counters Mode Description M1 M0 Mode 0 0 Mode Mode Mode Mode 3 Mode 0 Putting either timer/counter into mode 0 configures 8-bit timer/counter with a ...
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... This requirement imposes an obligation on the programmer to issue two instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has ...
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Interrupt Enable 0 Register (IEN0): 0xA8 MSB EAL WDT Bit Symbol IEN0.7 EAL EAL = 0 – disable all interrupts. IEN0.6 WDT Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before ...
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Interrupt Priority 0 Register (IP0): 0xA9 MSB – WDTS Bit Symbol IP0.6 WDTS Watchdog timer status flag. Set when the watchdog timer has expired. The internal reset will be generated, but this bit will not be cleared by the reset. ...
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... User (USR) Ports The 73S1217F includes 8 pins of general purpose digital I/O (GPIO). On reset or power-up, all USR pins are inputs until they are configured for the desired direction. The pins are configured and controlled by the USR70 and UDIR70 SFRs. Each pin declared as USR can be configured independently as an input ...
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External Interrupt Control Register (USRIntCtl1) : 0xFF90 MSB – U1IS.6 External Interrupt Control Register (USRIntCtl2) : 0xFF91 MSB – U3IS.6 External Interrupt Control Register (USRIntCtl3) : 0xFF92 MSB – U5IS.6 External Interrupt Control Register (USRIntCtl4) : 0xFF93 MSB – U7IS.6 ...
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Real-Time Clock with Hardware Watchdog (RTC) Figure 10 shows the block diagram of the Real Time Clock. The RTC block uses the 32768Hz oscillator signal and divider logic to produce 0.5-second time marks. The time marks are used to ...
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... In addition to the basic software watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, hardware watchdog timer (WDT) is included with the 73S1217F RTC. The Watch Dog timer will give the MPU ½ second to respond to the RTC Interrupt. If the processor does not perform an RTC Interrupt service, a full RESET will be performed. The RTC interrupt is connected to the core interrupt “ ...
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There are 3 sets of registers to load the RTC 24-bit accumulator, 32-bit counter and 23-bit trim registers. The registers are loaded when the RTCLD bit is set in RTCCtl. Register RTCCnt3 RTCCnt[31:24] Register Table 57: The 24-bit RTC Trim ...
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... Analog Voltage Comparator The 73S1217F includes a programmable comparator that is connected to the ANA_IN pin. The comparator can be configured to trigger an interrupt if the input voltage rises above or falls below a selectable threshold voltage. The comparator control register should not be modified when the analog interrupt (ANAIEN bit in the INT6Ctl generated when modifying the threshold ...
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External Interrupt Control Register (INT6Ctl): 0xFF95 MSB – – Bit Symbol INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. 2 INT6Ctl.3 I2CIEN I C interrupt enabled. 2 INT6Ctl.2 I2CINT I C interrupt ...
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... LED Driver The 73S1217F provides a single dedicated output pin for driving an LED. The LED driver pin can be configured as a current source that will pull to ground to drive an LED that is connected to VDD without the need for an external current limiting resistor. This pin may be used as general purpose output with the programmed pull-down current and a strong (CMOS) pull-up, if enabled ...
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... I C Master Interface The 73S1217F includes a dedicated fast mode, 400kHz I or write bytes of data per data transfer frame. The MPU communicates with the interface through six dedicated SFR registers: • Device Address (DAR) • Write Data (WDR) • Secondary Write Data (SWDR) • ...
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Figure 11 shows the timing of the I Transfer length (CSR bit0) Start I2C (CSR bit1) I2C_Interrupt SDA Device Address MSB SCL START condition Transfer length (CSR bit0) Start I2C (CSR bit1) I2C_Interrupt SDA Device Address MSB SCL START condition ...
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The following diagram shows the timing of the I Transfer length (CSR bit0) Start I2C (CSR bit1) I2c_Interrupt SDA Device Address MSB SCL START condition Transfer length (CSR bit0) Start I2C (CSR bit1) I2c_Interrupt SDA Device Address MSB SCL START ...
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Device Address Register (DAR): 0xFF80 MSB DVADR.6 DVADR.5 DVADR.4 DVADR.3 DVADR.2 Bit Symbol DAR.7 DAR.6 DAR.5 DVADR DAR.4 Slave device address. [0:6] DAR.3 DAR.2 DAR.1 DAR.0 I2CRW If set = 0, the transaction is a write operation. If set = ...
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I2C Secondary Write Data Register (SWDR): 0XFF82 MSB SWDR.7 SWDR.6 SWDR.5 Bit SWDR.7 SWDR.6 SWDR.5 SWDR.4 Second Data byte to be written to the I and Status register (CSR) is set = 1. SWDR.3 SWDR.2 SWDR.1 SWDR.0 I2C Read Data ...
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I2C Secondary Read Data Register (SRDR): 0XFF84 MSB SRDR.7 SRDR.6 SRDR.5 Bit SRDR.7 SRDR.6 SRDR.5 SRDR.4 Second Data byte to be read from the I and Status register (CSR) is set = 1. SRDR.3 SRDR.2 SRDR.1 SRDR.0 I2C Control and ...
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External Interrupt Control Register (INT6Ctl): 0xFF95 MSB – – Bit Symbol INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. INT6Ctl.3 I2CIEN When set = 1, the I When set =1, the I ...
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... Keypad Interface The 73S1217F supports a 30-button (6 row x 5 column) keypad (SPST Mechanical Contact Switches) interface using 11 dedicated I/O pins. Figure 13 shows a simplified block diagram of the keypad interface. Keypad Clock Column Value (1) KCOL Register Keypad Clock Row Value ...
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KORDERL / KORDERH. Key scanning is disabled at reset and must be enabled by firmware. When a valid key is detected, an interrupt is generated and ...
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KORDERL / H Registers: Column Scan Order More than 1 key No Deboucing Timer Is (are) the key(s) still released ? (*) Yes Figure 14: Keypad Interface Flow Chart Rev. 1.2 Keypad Initialization All Column Outputs = 0 Any Row ...
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Keypad Column Register (KCOL): 0xD1 This register contains the value of the column of a key detected as valid by the hardware. In bypass mode, this register firmware writes directly this register to carry out manual scanning. MSB – – ...
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Keypad Scan Time Register (KSCAN): 0xD3 This register contains the values of scanning time and debouncing time. MSB DBTIME.5 DBTIME.4 DBTIME.3 DBTIME.2 DBTIME.1 DBTIME.0 SCTIME.1 SCTIME.0 Bit Symbol KSCAN.7 DBTIME.5 KSCAN.6 DBTIME.4 De-bounce time in 4ms increments 4ms ...
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Keypad Control/Status Register (KSTAT): 0xD4 This register is used to control the hardware keypad scanning and detection capabilities, as well as the keypad interrupt control and status. MSB – – Bit Symbol KSTAT.7 – KSTAT.6 – KSTAT.5 – KSTAT.4 – ...
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... ROWSIZ.2 Bit Symbol KSIZE.7 – KSIZE.6 – KSIZE.5 ROWSIZ.2 Defines the number of rows in the keypad. Maximum number is 6 given KSIZE.4 ROWSIZ.1 the number of row pins on the package. Allows for a reduced keypad size for scanning. KSIZE.3 ROWSIZ.0 KSIZE.2 COLSIZ.2 Defines the number of columns in the keypad. Maximum number is 5 KSIZE ...
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Keypad Column MS Scan Order Register (KORDERH): 0xD7 MSB – 5COL.2 5COL.1 Bit Symbol KORDERH.7 – KORDERH.6 5COL.2 KORDERH.5 5COL.1 Column to scan 5 KORDERH.4 5COL.0 KORDERH.3 4COL.2 KORDERH.2 4COL.1 Column to scan 4 KORDERH.1 4COL.0 KORDERH.0 3COL.2 Column to ...
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... USB Interface The 73S1217F provides a single interface, full speed -12Mbps - USB device port as per the Universal Serial Bus Specification, Revision 2.0 (backward compatible with USB 1.1). USB circuitry gathers the transceiver, the Serial Interface Engine (SIE), and the data buffers. An internal pull- indicates that the device is a full speed device attached to the USB bus (allows full speed recognition by the host without adding any external components). When using the USB interface, V 3.0V – ...
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... USBPEN MISCtl1.0 USBCON Note: When using the USB on the 73S1217F, external 24Ω series resistors must be added to the D+ and D- signals to provide the proper impedance matching on these pins. The USB peripheral block is not able to support read or write operations to the USB SFR registers when the MPU clock is running at MPU clock rates of 12MHz or greater ...
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Clock Control Register (CKCON): 0x8E MSB – – Bit Symbol CKCON.7 – CKCON.6 – CKCON.5 – CKCON.4 – CKCON.3 – These three bits determine the number of wait states (machine cycles) to insert when accessing the USB SFRs: CKCON.2 CKWT.2 ...
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... Smart Card Interface Function The 73S1217F integrates one ISO-7816 (T=0, T=1) UART, one complete ICC electrical interface as well as an external smart card interface to allow multiple smart cards to be connected using the Teridian 73S8010x family of interface devices. Figure 16 shows the simplified block diagram of the card circuitry (UART + interfaces), with detail of dedicated XRAM registers ...
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... USR GPIO pins. The external 73S8010x devices directly connect the I/O (SIO) and clock (SCLK) signals and control 2 C interface. is handled via the I Figure 17 shows how multiple 73S8010x devices can be connected to the 73S1217F. VPC PRES PRES VCC ...
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... ISO 7816 UART An embedded ISO 7816 (hardware) UART is provided to control communications between a smart card and the 73S1217F MPU. The UART can be shared between the one built-in ICC interface and the external ICC interface. Selection of the desired interface is made via the external interface is handled by the I list of features for the ISO 7816 UART: • ...
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... TS byte that begins the ATR response response is not provided within the pre-programmed timeout period, an interrupt is generated and the firmware can then take appropriate action, including instructing the 73S1217F to begin a deactivation sequence. Once commanded, the deactivation sequencer goes through the power down sequence as defined in the ISO 7816-3 specification ...
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Firmware sets VCCSEL delay or Card Event IO RST CLK CMDVCCnB VCC t1: Time after either a “card event” occurs or firmware sets the VCCSela and VCCSelb bits to 0 (see t5, VCCOff_tmr) occurs until RST is ...
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... Support is provided for adding additional guard times between characters using the between the last byte received by the 73S1217F and the first byte transmitted by the 73S1217F using the Block Guard Time register (BGT) ...
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... Synchronous Operation Mode The 73S1217F supports synchronous operation. When sync mode is selected for either interface, the CLK signal is generated by the ETU counter. The values in FDReg, SCCLK, and obtain the desired sync CLK rate. There is only one ETU counter and therefore, in sync mode, the interface must be selected to obtain a smart card clock signal ...
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When the SCISYN or SCESNC bits (SPrtcol, bit 7, bit 5, respectively) are set, the selected smart card interface operates in synchronous mode and there are changes in the definition and behavior of pertinent register bits and associated circuitry. The ...
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... Note that in Sync mode input is sampled on the rising edge of CLK. IO changes on the falling edge of CLK, either from the card or from the 73S1217F. The RST signal to the card is directly controlled by the RSTCRD bit (non-inverted) via the MPU and is shown as an example of a possible RST pattern. ...
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CLK Data from Card -end of ATR IO RLength Count - was set for length of ATR RLength Interrupt CLK Stop CLK Stop Level IO Bit IODir Bit TX/RX Mode Bit TX = '1' 1. Interrupt generated when Rlength counter ...
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CLK Data from Card IO (Bit 8) RLength Count Rlen=8 RLength = 9 RLength Interrupt RX data Protection Bit Data (Bit 9) TX/RX Mode Bit TX = '1' 1._ Interrupt generated when Rlength counter is Max CLK RLength Count Rlen=8 ...
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Smart Card SFRs Smart Card Select Register (SCSel): 0xFE00 The Smart Card Select register is used to determine which smart card interface is using the ISO UART. The internal Smart Card has integrated 7816-3 compliant sequencer circuitry to drive ...
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Smart Card Interrupt Register (SCInt): 0xFE01 When the smart card interrupt is asserted, the firmware can read this register to determine the actual cause of the interrupt. The bits are cleared when this register is read. Each interrupt can be ...
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Smart Card Interrupt Enable Register (SCIE): 0xFE02 When set to 1, the respective condition can cause a smart card interrupt. When set the respective condition cannot cause an interrupt. When disabled, the respective bit in the Smart ...
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... If not set, the deactivation sequence shall start when the VCCTMR times out. VccCtl.3 VCCOK (Read only). Indicates that V VccCtl.2 – VccCtl.1 – This bit controls the power-off mode of the 73S1217F circuit power off normal operation. When in power down mode, VccCtl.0 SCPWRDN V DD application set, it has no effect until V 92 ...
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V Stable Timer Register (VccTmr): 0xFE04 CC A programmable timer is provided to set the time from activation start (setting the VCCSEL.1 and VCCSEL.0 bits to non-zero) to when VCC_OK is evaluated. VCC_OK must be true at the end of ...
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Card Status/Control Register (CRDCtl): 0xFE05 This register is used to configure the card detect pin (DETCARD) and monitor card detect status. This register must be written to properly configure Debounce, Detect_Polarity (= 1), and the pull- up/down ...
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TX Control/Status Register (STXCtl): 0xFE06 This register is used to control transmission of data to the smart card. Some control and some status bits are in this register. MSB I2CMODE – TXFULL Bit Symbol I2C Mode – When in sync ...
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STX Data Register (STXData): 0xFE07 MSB STXDAT.7 STXDAT.6 STXDAT.5 Bit STXData.7 STXData.6 STXData.5 Data to be transmitted to smart card. Gets stored in the TX FIFO and then extracted by the hardware and sent to the selected smart card. When ...
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SRX Control/Status Register (SRXCtl): 0xFE08 This register is used to monitor reception of data from the smart card. MSB BIT9DAT – Bit Symbol Bit 9 Data – When in sync mode and with MODE9/8B set, this bit will contain SRXCtl.7 ...
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SRX Data Register (SRXData): 0xFE09 MSB SRXDAT.7 SRXDAT.6 SRXDAT.5 SRXDAT.4 SRXDAT.3 SRXDAT.2 SRXDAT.1 SRXDAT.0 Bit SRXData.7 SRXData.6 SRXData.5 SRXData.4 (Read only) Data received from the smart card. Data received from the smart card gets stored in a FIFO that is ...
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Smart Card Control Register (SCCtl): 0xFE0A This register is used to monitor reception of data from the smart card. MSB RSTCRD – Bit Symbol 1 = Asserts the RST (set RST = 0) to the smart card interface ...
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External Smart Card Control Register (SCECtl): 0xFE0B This register is used to directly set and sample signals of External Smart Card interface. There are three modes of asynchronous operation, an “automatic sequence” mode, and bypass mode. Clock stop per the ...
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C4/C8 Data Direction Register (SCDIR): 0xFE0C This register determines the direction of the internal interface C4/C8 lines. After reset, all signals are tri-stated. MSB – – Bit Symbol SCDIR.7 – SCDIR.6 – SCDIR.5 – SCDIR.4 – SCDIR.3 C8D 1 = ...
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Protocol Mode Register (SPrtcol): 0xFE0D This register determines the protocol to be use when communicating with the selected smart card. This register should be updated as required when switching between smart card interfaces. MSB SCISYN MOD9/8B SCESYN Bit Symbol Smart ...
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SC Clock Configuration Register (SCCLK): 0xFE0F This register controls the internal smart card (CLK) clock generation. MSB LSB – – ICLKFS.5 ICLKFS.4 ICLKFS.3 ICLKFS.2 ICLKFS.1 ICLKFS.0 Bit Symbol SCCLK.7 – SCCLK.6 – SCCLK.5 ICLKFS.5 Internal Smart Card CLK Frequency Select ...
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Parity Control Register (SParCtl): 0xFE11 This register provides the ability to configure the parity circuitry on the smart card interface. The settings apply to both integrated smart card interfaces. MSB – DISPAR BRKGEN BRKDET RETRAN DISCRX Bit Symbol SParCtl.7 – ...
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Byte Control Register (SByteCtl): 0xFE12 This register controls the processing of characters and the detection of the TS byte. When receiving, a Break is asserted at 10.5 ETU after the beginning of the start bit. Break from the card is ...
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... MSCLK by 2 times the Fi/Di ratio specified by the codes below. For example 0001 and DI = 0001, the ratio of Fi/Di is 372/1. Thus, the ETU divider is configured to divide 372 = 744. The maximum supported F/D ratio is 4096. Table 98: Divider Ratios Provided by the ETU Counter ...
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Table 99: Divider Values for the ETU Clock Fi code 0000 Di 372 F→ code D↓ 0001 1 744 0010 2 372 0011 4 186 0100 8 93 1000 12 62 0101 16 47 1001 20 37 0110 32 23 ...
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CRC MS Value Registers (CRCMsB): 0xFE14 MSB CRC.15 CRC.14 MSB CRC.7 CRC.6 The 16-bit CRC value forms the TX CRC word in TX mode (write value) and the RX CRC in RX mode (read value). The initial value of CRC ...
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Block Guard Time Register (BGT): 0xFE16 This register contains the Extra Guard Time Value (EGT) most-significant bit. The Extra Guard Time indicates the minimum time between the leading edges of the start bit of consecutive characters. The delay is depends ...
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... These registers (BWTB0, BWTB1, BWTB2, BWTB3) are used to set the Block Waiting Time(27:0) (BWT). All of these parameters define the maximum time the 73S1217F will have to wait for a character from the smart card. These registers serve a dual purpose. When T=1, these registers are used to set up the block wait time ...
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ATR Timeout Registers (ATRLsB): 0xFE20 MSB ATRTO.7 ATRTO.6 ATRTO.5 MSB ATRTO.15 ATRTO.14 ATRTO.13 These registers (ATRLsB and ATRLsB) form the ATR timeout (ATRTO [15:0]) parameter. Time in ETU between the leading edge of the first character and leading edge of ...
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... Data Sheet Shaded locations indicate functions that are not provided in sync mode. Name Address b7 SCSel FE00 SCInt FE01 WAITTO/ RLIEN SCIE FE02 WTOI/ RLIEN VccCtl FE03 VCCSEL.1 VccTmr FE04 CRDCtl FE05 DEBOUN STXCtl FE06 I2CMODE STXData FE07 SRXCtl FE08 BIT9DAT ...
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... Note: The V Fault factory default can be set to any threshold as defined by bits VDDFTH(2:0). The DD 73S1217F has the capability to burn fuses at the factory to set the factory default to any of these voltages. Contact Teridian for further details. Rev. 1.2 falls below the V DD 0x00 Table 115: The VDDFCtl Register – ...
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... SW_MOM SW_MOM SW_MOM SW_MOM OPTIONAL LCD DISPLAY SYSTEM 16 CHARACTER BY 2 LINES U2 Figure 27: 73S1217F Typical Application Schematic (Handheld USB PINpad, with Combo USB-Bus and Self-powered Configuration) 114 12.000MHz C2 C3 22pF 22pF D1 LED VDD ...
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... GND GND 3 R18 R19 +5VDC VCC 6 GND C27 USB_CONN_4 0.1uF Figure 28: 73S1217F Typical Application Schematic (USB Transparent Reader and USB Key Configuration) Rev. 1.2 R16 Y2 1M 12.000MHz C21 C22 22pF 22pF VDD U4 69 SLUG 18 68 TXD VDD 19 67 ...
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... Electrical Specification 3.1 Absolute Maximum Ratings Operation outside these rating limits may cause permanent damage to the device. The smart card interface pins are protected against short circuits to V Parameter DC Supply voltage Supply Voltage V PC Supply Voltage V BUS Supply Voltage V BAT Storage Temperature ...
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Digital IO Characteristics These requirements pertain to digital I/O pin types with consideration of the specific pin function and configuration. The Row pins have 100KΩ pull-ups. Symbol Parameter Voh Output level, high Vol Output level, low Vih Input voltage, ...
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Oscillator Interface Requirements Symbol Parameter Low-Power Oscillator Requirements. No External Load Beside The Crystal And Capacitor Is Permitted On Xout32 Pxtal Power in crystal IIL Input Leakage Current High-frequency oscillator (XIN) Parameters. XIN is used as input for external ...
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USB Interface Requirements Parameter Receiver Parameters Differential input sensitivity Differential common mode range Single ended receiver threshold Transmitter Levels Low Level Output Voltage High Level Output Voltage Output Resistance (1) Driver output resistance PD Pullup Resistor (to VDD) Transceiver ...
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Parameter C = 50pf, series 24Ω, 1% source termination resistor included L Rise Time USBTR Fall Time USBTF Rise/fall time matching TRFM Output signal crossover VCRS voltage Source Jitter to Next TDJ1 Transition Source Jitter For Paired TDJ2 Transitions Receiver ...
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Smart Card Interface Requirements Symbol Parameter Card Power Supply (V ) Regulator CC General conditions, -40°C < T < 85°C, 4.75V < V Card supply Voltage V including ripple and CC noise V V Ripple CCrip CC Card supply ...
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... Output rise time, fall times Input rise, fall times Internal pull-up resistor PU FD Maximum data rate MAX Reset and Clock for Card Interface, RST, CLK V Output level, high OH V Output level, low OL Output voltage when outside V INACT of session ...
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DC Characteristics Symbol Parameter Supply Current @ V (V and V unconnected) BUS BAT Supply Current @ V (V and V unconnected) BUS BAT I PC Supply Current @ V (V and V unconnected) BUS BAT Supply Current @ ...
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BUS Supply Current @ V 6. 0V) BUS V V Supply Voltage DD DD Supply Current I DD_IN (pins 28 and 40) Supply Current – pin 68 I (available to external DD_OUT circuitry) I ...
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Current Fault Detection Circuits Symbol Parameter IV V over current fault Pmax P I VDD over-current limit DDmax I Card overcurrent fault CCF I Card overcurrent fault CCF1P8 Rev. 1.2 Condition Min Typ 1.8V 60 ...
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Equivalent Circuits X12LIN ESD ENABLE ENABLEb X32LIN ESD 126 VDD Figure 29: 12 MHz Oscillator Circuit VDD >1MEG Figure 30: 32KHz Oscillator Circuit X12OUT ESD To circuit X32OUT ESD To circuit Rev. 1.2 ...
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Output Disable Data From circuit To circuit Output Disable Data From circuit Rev. 1.2 VDD STRONG PFET STRONG NFET Figure 31: Digital I/O Circuit VDD STRONG PFET STRONG NFET Figure 32: Digital Output Circuit PIN ESD PIN ESD 127 ...
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Pull-up Disable Output Disable Data From circuit To circuit Figure 33: Digital I/O with Pull Up Circuit Output Disable Data From circuit To circuit Pull-down Enable Figure 34: Digital I/O with Pull Down Circuit 128 VDD VERY WEAK PFET STRONG ...
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To circuit Pull-up Disable Output Disable Data From circuit To circuit Pull-down Enable Rev. 1.2 Figure 35: Digital Input Circuit STRONG PFET STRONG NFET Figure 36: OFF_REQ Interface Circuit PIN ESD VDD VERY WEAK PFET ESD PIN ESD VERY WEAK ...
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Pull-up Disable Output Disable Data From circuit To circuit Output Disable Data From circuit To circuit 130 STRONG PFET STRONG NFET Figure 37: Keypad Row Circuit VDD 1200 OHMS MEDIUM PFET STRONG NFET Figure 38: Keypad Column Circuit VDD 100k ...
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Pullup Disable Data From circuit To circuit Current Value Control PIN Figure 40: Test and Security Pin Circuit Rev. 1.2 VDD STRONG PFET STRONG NFET Figure 39: LED Circuit This buffer has a special input threshold: Vih>0.7*VDD ...
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From circuit 132 To Comparator Input PIN ESD Figure 41: Analog Input Circuit VCC Figure 42: Smart Card Output Circuit STRONG ESD PFET PIN ESD STRONG NFET Rev. 1.2 ...
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From circuit To circuit To circuit Pull-down Enable Rev. 1.2 STRONG PFET 125ns DELAY STRONG NFET Figure 43: Smart Card I/O Circuit VERY WEAK NFET Figure 44: PRES Input Circuit VCC RL=11K ESD IO PIN ESD VDD ESD PIN ESD ...
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RP_ENb DP_OUT DP_IN RCV_IN DM_IN DM_OUT OUTPUT ENABLEb PIN 134 VDD VDD ZOUT= 20Ω OUTPUT ENABLEb IN_P IN_N VDD ZOUT= 20Ω Figure 45: USB Circuit VPC R= 24kΩ ESD Figure 46: ON_OFF Input Circuit 1500 Ω DP ESD DM ESD ...
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... GND VDD 28 USR5 29 USR4 30 USR3 31 USR2 32 ROW3 33 USR1 34 Rev. 1.2 CAUTION: Use handling procedures necessary for a static sensitive component TERIDIAN 73S1217F Figure 47: 73S1217F Pinout Figure 47: 73S1217F Pinout 68 VDD GND 67 LIN 66 VPC 65 VBAT 64 ON_OFF 63 VBUS AUX1 60 AUX2 59 VCC 58 RST 57 GND ...
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... Notes: 6.3mm x 6.3mm exposed pad area must remain UNCONNECTED (clear of PCB traces or vias). Controlling dimensions are in mm. vias). Controlling dimensions are in mm. 8.00 7. TOP VIEW TOP VIEW 8.00 0.42 0.24/0.60 6.30 6.15/6.45 0.45 0.42 0.24/0.60 6.30 6.15/6.45 6.40 BOTTOM VIEW Figure 48: 73S1217F 68 QFN Mechanical Drawing 136 7.75 8.00 PIN#1 ID R0. 0.20 2 0.15/0.25 3 6.40 8.00 0.40 FOR ODD TERMINAL/SIDE 0.65 0.85 0.2 0.00/0.05 12° SEATING PLANE SIDE VIEW 0 ...
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... Evaluation Board User’s Guide 73S12xxF Software User’s Guide 73S12xxF Synchronous Card Design Application Note 7 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73S1217F, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 ...
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... MCLK = 96MHz are shown in Table 11.” In and power applied to the VBUS input, the 73S1217F will go into either standby mode or power “OFF” mode. If system power is provided by, VBUS or the ON/OFF circuitry is in the “ON” state, the MPU core will placed into standby mode.” ...
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PGADDR (see detailed description above).” FUSECtl bit description to TRIMPCtl Added the RTCTrim0 and ACOMP registers. Deleted the OMP, VRCtl, LEDCal and LOCKCtl registers the paragraphs about MPU clock rates ...
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