73S8009CN Maxim, 73S8009CN Datasheet
73S8009CN
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73S8009CN Summary of contents
Page 1
... The 73S8009CN features an ON/OFF pin suitable to connect to a “push-on/push-off” main system switch. When the 73S8009CN is “OFF,” the typical current drawn from VPC is 10nA. For applications that do not implement any ON/OFF system switch, the ON/OFF input pin can be driven from a digital output of the host processor ...
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... V CC Regulator and Vcc Status SHUTDOWN Logic Card I/O Buffer and Signal Logic To Internal Digital Logic 3.3V Regulator GND V P 4.7µF Figure 1: 73S8009CN Block Diagram DS_8009CN_026 ON/OFF Debounce and Latch OFF_REQ 100K OFF_ACK Delay/ RDY Debounce Circuit V CC 0.47µF OFF I/O RST CLK DP AUX1 ...
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... Digital Signals Characteristics ............................................................................................... 12 2.5 DC Characteristics ................................................................................................................ 13 2.6 Voltage / Temperature Fault Detection Circuits ...................................................................... 13 2.7 Thermal Characteristics ........................................................................................................ 13 3 Applications Information ............................................................................................................. 13 3.1 Example 73S8009CN Schematics ......................................................................................... 13 3.2 Power Supply and Converter ................................................................................................. 16 3.3 Interface Function - ON/OFF Modes ...................................................................................... 16 3.4 System Controller Interface ................................................................................................... 18 3.5 Card Power Supply and Voltage Supervision......................................................................... 18 3.6 Activation and De-activation Sequence ................................................................................. 19 OFF and Fault Detection ....................................................................................................... 20 3 ...
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... Figures Figure 1: 73S8009CN Block Diagram ...................................................................................................... 2 Figure 2: 73S8009CN 32-Pin QFN Pinout ................................................................................................ 5 Figure 3: Typical 73S8009CN Application Schematic with a Main System Switch ................................... 14 Figure 4: Typical 73S8009CN Application Schematic without a Main System Switch .............................. 15 Figure 5: Activation Sequence ............................................................................................................... 19 Figure 6: Deactivation Sequence ........................................................................................................... 20 Figure 7: OFF Activity ............................................................................................................................ 20 Figure 8: CS Timing Definitions .............................................................................................................. 21 Figure 9: I/O and I/OUC State Diagram .................................................................................................. 22 Figure 10: I/O – ...
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... DS_8009CN_026 1 Pinout The 73S8009CN is supplied as a 32-pin QFN package. 1 I/OUC AUX1UC 2 AUX2UC 3 4 CMDVCC5 CMDVCC3 5 RSTIN 6 CLKIN 7 RDY 8 Figure 2: 73S8009CN 32-Pin QFN Pinout Table 1 describes the pin functions for the device. Pin Pin Type Name Number Card Interface I AUX1 21 IO ...
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... Signals RDY and OFF are disabled to prevent a low output and the internal pull-up resistors are disconnected. Should be tied to VDD when a single 73S8009CN is used. Figure 12 Interrupt signal to the processor. Active Low - Multi-function indicating fault conditions and card presence. Open drain output configuration – ...
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... Can be controlled by a host processor digital output. Figure 19 Digital output. Request to the host system controller to turn the 73S8009CN off. If ON_OFF switch is closed (to ground) for de-bounce duration and circuit is “on,” OFF_REQ will go high (request to turn OFF). Connected to OFF_ACK via 100k Ω internal resistor. ...
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... Data Sheet Pin Pin Type Name Number Power Supply and Ground VDD 29 PSO VPC 26 PSI LIN 27 PSI VP 15 PSO GND 28, 31 GND 8 Equivalent Circuit Figure 13 System interface supply voltage output and supply voltage for companion controller circuit (40mA maximum source capability). Requires a minimum of two 0.1µ ...
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... Thermal characteristics 2.1 Absolute Maximum Ratings Table 2 lists the maximum operating conditions for the 73S8009CN. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. Table 2: Absolute Maximum Device Ratings ...
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... Data Sheet 2.3 Smart Card Interface Requirements Table 4 lists the 73S8009CN Smart Card interface requirements. Table 4: DC Smart Card Interface Requirements Symbol Parameter Card Power Supply (V ) Regulator CC General Conditions: -40C < 85C, 2.7 V < V Card supply voltage V CC including ripple and noise V V ripple ...
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... For I/O, AUX1, AUX2 80pF, 10% to 90%. L For I/OUC, AUX1UC, AUX2UC, CL=50Pf, 10% to 90%. Output stable for >200ns Edge from master to slave, measured at 50% 0 < Vdm, Vdp <3.3V, VCC=5V, SC/USB =1 0 < Vdm, Vdp < 3.3V, VCC=5V, SC/USB =0 73S8009CN Data Sheet Min Nom Max – – 0. +0.1 ...
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... Output rise time, fall time R F δ Duty cycle for CLK 2.4 Digital Signals Characteristics Table 5 lists the 73S8009CN digital signals characteristics. Table 5: Digital Signals Characteristics Symbol Parameter Digital I/O (except for I/OUC, AUX1UC, AUX2UC; see Smart Card Interface Requirements for those specifications) V ...
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... Example 73S8009CN Schematics Figure 3 shows a typical application schematic for the implementation of the 73S8009CN with a main system switch. Figure 4 shows a typical application schematic for the implementation of the 73S8009CN without a main system switch. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information ...
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... VDD - 3.3V, +/- 0.3V, 40mA max. Schematic assumes VDD supplies power to the host controller. Requires min two 0.1µF caps to gnd) 6) The RDY signal is optional. A short delay before releasing RSTIN should suffice for the RDY signal function. Figure 3: Typical 73S8009CN Application Schematic with a Main System Switch 14 VDD VPC ...
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... VDD - 3.3V, +/- 0.3V, 40mA max. Schematic assumes VDD is monitored by the host controller. Requires min two 0.1µF caps to gnd) 6) Resistors are necessary to provide isolation between powered host and "OFF" 73S8009CN. Signals should be driven low in this condition. 7) The RDY signal is optional. A short delay before releasing RSTIN should suffice for the RDY signal function ...
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... OFF). When the 73S8009CN is OFF, the host should drive the ON/OFF pin low to initiate the turn ON process. The signal must remain low until the V goes to 3.3V. The 73S8009CN is now ON and the ON/OFF pin should be driven back high. To turn off the 73S8009CN, the host should drive the ON/OFF signal low until the V 73S8009CN is now OFF and the ON/OFF pins should be driven back high ...
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... V DD activated. 4. When the 73S8009CN is powered OFF, the host will not be able to detect a card event (card insertion/removal). If this function is necessary, then the host must monitor the card connector switch separately. 5. For systems that do not use VDD to power the host controller, the host interface signals must operate at 3 ...
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... The smart card pass through signals are enabled when the RDY conditions are met. 3.5 Card Power Supply and Voltage Supervision The 73S8009CN smart card interface IC incorporates an LDO voltage regulator for the card power supply conversion uses an internal LDO). The voltage output is controlled by the digital ...
Page 19
... The host controller is fully responsible for the activation sequencing of the smart card signals CLK, RST, I/O, AUX1 and AUX2. All these signals are held low by the 73S8009CN when the card is in the de- activated state. Upon card activation (the fall of CMDVCC (#/%)), all the signals are held low by the 73S8009CN until RDY goes high ...
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... Data Sheet CMDVCC RST CLK I/O VCC_ON VCC t1 OFF and Fault Detection 3.7 There are two different cases that the system controller can monitor the OFF signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. Outside a card session: In this condition, CMDVCC (#/%) are always high, OFF is low if the card is not present, and high if the card is present ...
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... With regard to de-activation, CS does not affect the operation of the fault sensing circuits and card sense input. CS does not affect the action of SC/USB. CS OFF, I/OUC, AUX1UC, AUX2UC CONTROL SIGNALS Rev. 1 HI-Z STATE FUNCTIONAL Figure 8: CS Timing Definitions 73S8009CN Data Sheet t DZ HI-Z STATE ...
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... Data Sheet 3.9 I/O Circuitry and Timing The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are in high when the activation sequencer turns on the I/O reception state. See the Activation and De-activation Sequence section for more details on when the I/O reception is enabled. The states of I/OUC, AUX1UC, and AUX2UC are high after power on reset ...
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... DS_8009CN_026 The delay between the I/O signals is shown in Figure 10. I/O I/OUC Delay from I/O to I/OUC: Delay from I/OUC to I/O: Figure 10: I/O – I/OUC Delays - Timing Diagram Rev. 1.4 t I/O_HL t I/O_LH t = 100ns I/O_HL t = 100ns I/OUC_HL 73S8009CN Data Sheet t t I/OUC_HL I/OUC_LH t = 15ns I/O_LH t = 15ns I/OUC_LH 23 ...
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... Data Sheet 4 Equivalent Circuits This section provides illustrations of circuits equivalent to those described in the Pinout section. PIN Output Disable circuit Figure 12: Open Drain type – OFF and RDY PIN Figure 13: Power Input/Output Circuit, VDD, LIN, VPC, VCC 24K ESD Figure 11: On_Off Pin ...
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... Figure 16: Smart Card RST Driver Circuit Rev. 1.4 TO AUX1 2 ohms or AUX2 ESD Figure 14: USB – DM, DP Pins VCC VERY STRONG PFET VERY STRONG NFET VCC STRONG PFET STRONG NFET 73S8009CN Data Sheet PAD ESD CLK PIN ESD ESD RST PIN ESD 25 ...
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... Data Sheet From circuit To circuit Figure 17: Smart Card IO, AUX1, and AUX2 Interface Circuit From circuit To circuit Figure 18: Smart Card IOUC, AUX1UC and AUX2UC Interface Circuit 26 VCC STRONG PFET 400ns DELAY STRONG NFET ESD VDD STRONG PFET 400ns DELAY STRONG NFET ...
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... VERY WEAK PFET VERY WEAK NFET SC/USB have the pull-up enabled. Figure 19: General Input Circuit VDD STRONG PFET STRONG NFET Ω Ω Ω Ω Figure 20: OFF_REQ Interface Circuit 73S8009CN Data Sheet ESD PIN ESD ESD PIN ESD 100k ohm To OFF_ACK pad 27 ...
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... Data Sheet 5 Mechanical Drawing 5 2 TOP VIEW 0.2 MIN. 0.35 / 0.45 Figure 21: 32-Pin QFN Package Dimensions 28 / 0.85 NOM. 0.9MAX. 3.0 / 3.75 0.18 / 0.3 1.5 / 1.875 0.25 0.5 BOTTOM VIEW DS_8009CN_026 0.00 / 0.005 0.20 REF. SEATING PLANE SIDE VIEW CHAMFERED 0.30 Rev. 1.4 ...
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... DS_8009CN_026 6 Ordering Information Table 9 lists the order numbers and packaging marks used to identify 73S8009CN products. Table 9: Order Numbers and Packaging Marks Part Description 73S8009CN-32QFN 32-pin Lead-Free QFN 73S8009CN-32QFN 32-pin Lead-Free QFN Tape / Reel 7 Related Documentation The following 73S8009CN document is available from Teridian Semiconductor Corporation: 73S8009CN 32QFN Demo Board User’ ...
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... Data Sheet Revision History Revision Date 1.0 10/23/2007 First publication. 1.1 11/6/2007 Added the Related Documentation section and the Contact Information section. Miscellaneous editorial changes. Change the name of the “SC_USB” pin to “SC/USB”. 1.2 1/21/2008 Changed the dimension of the bottom view 32-pin QFN package. ...