MAX7359 Maxim, MAX7359 Datasheet - Page 15

• Manufacturer Part Number: MAX7359
• Description: The MAX7359 I²C interfaced peripheral provides microprocessors with management of up to 64 key switches
• Manufacturer: Maxim

The acknowledge bit is a clocked 9th bit (Figure 4),
which the recipient uses to handshake receipt of each
byte of data. Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7359, the MAX7359
generates the acknowledge bit because the MAX7359
is the recipient. When the MAX7359 is transmitting to
the master, the master generates the acknowledge bit
because the master is the recipient.
The MAX7359 has a 7-bit long slave address (Figure 5).
The bit following a 7-bit slave address is the R/W bit,
which is low for a write command and high for a read
command.
The first 4 bits (MSBs) of the MAX7359 slave address
are always 0111. Slave address bits A3, A2, and A1
correspond, by the matrix in Table 10, to the states of
the device address input AD0, and A0 corresponds to
the R/W bit. The AD0 input can be connected to any of
four signals: GND, V
ble slave address pairs, allowing up to four MAX7359
devices to share the bus. Because SDA and SCL are
dynamic signals, care must be taken to ensure that AD0
transitions no sooner than the signals on the SDA and
SCL pins.
Figure 4. Acknowledge
Figure 5. Slave Address
TRANSMITTER
RECEIVER
SDA
SCL
SCL
SDA
SDA
BY
BY
______________________________________________________________________________________
CC
CONDITION
START
MSB
, SDA, or SCL, giving four possi-
S
0
1
Slave Addresses
Acknowledge
1
1
1
Key Switch Controller/GPO
2-Wire Interfaced Low-EMI
2
A3
The MAX7359 monitors the bus continuously, waiting for
a START condition followed by its slave address. When
the MAX7359 recognizes its slave address, it acknowl-
edges and is then ready for continued communication.
The MAX7359 features a 20ms minimum bus timeout on
the 2-wire serial interface, largely to prevent the
MAX7359 from holding the SDA I/O low during a read
transaction if the SCL hangs for any reason before a seri-
al transaction has been completed. Bus timeout operates
by causing the MAX7359 to internally terminate a serial
transaction, either read or write, if SCL low exceeds
20ms. After a bus timeout, the MAX7359 waits for a valid
START condition before responding to a consecutive
transmission. This feature can be enabled or disabled
under user control by writing to the configuration register
(Table 4).
Table 10. 2-Wire Interface Address Map
PIN AD0
GND
SDA
V
SCL
CC
A2
A7
0
0
0
0
LSB
A1
8
CLOCK PULSE FOR
A6
1
1
1
1
ACKNOWLEDGE
R/W
A5
1
1
1
1
DEVICE ADDRESS
A4
1
1
1
1
ACK
9
A3
0
0
1
1
Bus Timeout
A2
0
1
0
1
A1
0
0
0
0
R/W
R/W
R/W
R/W
A0
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