MAX902ESD+T Maxim Integrated Products, MAX902ESD+T Datasheet - Page 10

• Manufacturer Part Number: MAX902ESD+T
• Description: IC COMPARATOR VOLT 14-SOIC
• Manufacturer: Maxim Integrated Products
• Type: General Purposer

Specifications of MAX902ESD+T

• Number Of Elements: 2
• Output Type: TTL
• Voltage - Supply: 5 V ~ 10 V, ±2.5 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

V
V
V
t
t
pd+
pd-
OS
IN
OD
High-Speed, Low-Power Voltage Comparators
Input Offset Voltage: Voltage applied
between the two input terminals to obtain
TTL-logic threshold (+1.4V) at the
output.
Input Voltage Pulse Amplitude: Usually
set to 100mV for comparator
specifications.
Input Voltage Overdrive: Usually set to
5mV and in opposite polarity to V
comparator specifications.
Input-to-Output High Delay: The
propagation delay measured from the
time the input signal crosses the input
offset voltage to the TTL-logic threshold
of an output low-to-high transition
Input-to-Output Low Delay: The
propagation delay measured from the
time the input signal crosses the input
offset voltage to the TTL-logic threshold
of an output high-to-low transition.
_______________________________________________________________________________________
IN
for
t
t
t s
t h
t pw (D)
pd+ (D)
pd- (D)
Latch Disable-to-Output High Delay:
The propagation delay measured from
the latch-signal crossing the TTL
threshold in a low-to-high transition to
the point of the output crossing TTL
threshold in a low-to-high transition.
Latch Disable-to-Output Low Delay:
The propagation delay measured from
the latch-signal crossing the TTL
threshold in a low-to-high transition to
the point of the output crossing TTL
threshold in a high-to-low transition.
Minimum Setup Time: The minimum
time before the negative transition of the
latch signal that an input signal change
must be present in order to be acquired
and held at the outputs.
Minimum Hold Time: The minimum time
after the negative transition of the latch
signal that an input signal must remain
unchanged in order to be acquired and
held at the output.
Minimum Latch-Disable Pulse Width:
The minimum time that the latch signal
must remain high in order to acquire and
hold an input-signal change.
Definitions of Terms
9