MAX4821 Maxim, MAX4821 Datasheet
MAX4821
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MAX4821 Summary of contents
Page 1
... Each data bit in the shift reg- ister corresponds to a specific output, allowing indepen- dent control of all outputs. The MAX4821 features a 4-bit (A0, A1, A2, LVL) paral- lel-input interface. The first three bits (A0, A1, A2) deter- mine the output address, and the fourth bit (LVL) determines whether the selected output is switched on or off ...
Page 2
... Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
Page 3
... Rise Time (DIN, SCLK, CS, SET, RESET) Fall Time (DIN, SCLK, CS, RESET, SET) RESET Min Pulse Width SET Min Pulse Width PARALLEL TIMING (MAX4821) Turn-On Time Turn-Off Time LVL Setup Time LVL Hold Time Address to CS Setup Time Address to CS Hold Time ...
Page 4
Cascadable Relay Drivers with Serial/Parallel Interface ( -40°C to +85°C, unless otherwise noted. Typical values are at T COM CC A SUPPLY CURRENT vs. SUPPLY VOLTAGE 25 ALL LOGIC INPUTS = 0 20 ...
Page 5
... SCLK’s rising edge. Drive CS from low CS to high to latch the data to the registers and activate the appropriate relays. MAX4821: Drive CS low to select the device and set level on LVL. Drive CS from low to high to latch the address and level data to the output. DIN ...
Page 6
... Digital Address “2” Input. (See Table 2 for address mapping.) EP Exposed Pad. Connect exposed pad to GND. The MAX4821 features a 4-bit (A0, A1, A2, LVL) parallel input interface. The three bits (A0, A1, A2) determine the output address, and LVL determines whether the selected output is switched on or off. Data is latched to the outputs when CS transitions from low to high ...
Page 7
... Address data entered after CS is pulled low is not reflected in the state of the outputs following the next low-to-high transition on CS (Figure 2). t CSW t CSH OFF OUT5 OUT6 OUT7 Parallel Interface (MAX4821) t CSO D7 OUT8 7 ...
Page 8
... Cascadable Relay Drivers with Serial/Parallel Interface LVL V OUT Figure 2. Parallel Interface Timing Diagram (MAX4821 only 0.1μ DIN DIN DOUT MAX4820 OUT1 SCLK SCLK OUT8 CS GND PGND CS Figure 3. Daisy-Chain Configuration 8 _______________________________________________________________________________________ Table 2. Parallel Interface Address Map ...
Page 9
... GND PGND _______________________________________________________________________________________ with Serial/Parallel Interface The MAX4820/MAX4821 feature built-in inductive kick- back protection to reduce the voltage spike on OUT_ generated by a relay’s coil inductance when the output is suddenly switched off. Internal diodes connected from each output to COM allow the inductor current to flow back to the supply ...
Page 10
... SCLK RESET SET LVL ______________________________________________________________________________________ COM MAX4820 PARALLEL REGISTER 8-BIT SHIFT REGISTER PGND GND COM MAX4821 PARALLEL LATCH 4-TO-8 DECODER GND PGND Functional Diagrams OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 ...
Page 11
... RoHS status. PACKAGE TYPE 20 TQFN-EP 20 TSSOP-EP + OUT1 OUT1 CC OUT2 SET 2 19 OUT2 PGND RESET 3 18 PGND OUT3 OUT3 MAX4821 OUT4 LVL 5 16 OUT4 COM COM OUT5 OUT5 OUT6 OUT6 PGND GND 9 12 PGND ...
Page 12
... Added Reflow Temperature to the Absolute Maximum Ratings section. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...