MAX9122 Maxim, MAX9122 Datasheet

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MAX9122

Manufacturer Part Number
MAX9122
Description
The MAX9121/MAX9122 quad low-voltage differential signaling (LVDS) differential line receivers are ideal for applications requiring high data rates, low power, and low noise
Manufacturer
Maxim
Datasheet

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The MAX9121/MAX9122 quad low-voltage differential sig-
naling (LVDS) differential line receivers are ideal for appli-
cations requiring high data rates, low power, and low
noise. The MAX9121/MAX9122 are guaranteed to receive
data at speeds up to 500Mbps (250MHz) over controlled-
impedance media of approximately 100Ω. The transmis-
sion media may be printed circuit (PC) board traces or
cables.
The MAX9121/MAX9122 accept four LVDS differential
inputs and translate them to LVCMOS outputs. The
MAX9122 features integrated parallel termination resis-
tors (nominally 107Ω), which eliminate the requirement
for four discrete termination resistors and reduce stub
lengths. The MAX9121 inputs are high impedance and
require an external termination resistor when used in a
point-to-point connection.
The devices support a wide common-mode input range of
0.05V to 2.35V, allowing for ground potential differences
and common-mode noise between the driver and the
receiver. A fail-safe feature sets the output high when the
inputs are open, or when the inputs are undriven and
shorted or parallel terminated. The EN and EN inputs con-
trol the high-impedance output. The enables are common
to all four receivers. Inputs conform to the ANSI TIA/EIA-
644 LVDS standard. Flow-through pinout simplifies PC
board layout and reduces crosstalk by separating the
LVDS inputs and LVCMOS outputs. The MAX9121/
MAX9122 operate from a single +3.3V supply, and are
specified for operation from -40°C to +85°C. These
devices are available in 16-pin TSSOP and SO packages.
Refer to the MAX9123 data sheet for a quad LVDS line dri-
ver with flow-through pinout.
19-1909; Rev 0; 6/01
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Integrated Termination and Flow-Through Pinout
Digital Copiers
Laser Printers
Cellular Phone Base Stations
Add/Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches/Routers
Backplane Interconnect
Clock Distribution
________________________________________________________________ Maxim Integrated Products
General Description
Applications
Quad LVDS Line Receivers with
o Integrated Termination Eliminates Four External
o Flow-Through Pinout
o Pin Compatible with DS90LV048A
o Guaranteed 500Mbps Data Rate
o 300ps Pulse Skew (max)
o Conform to ANSI TIA/EIA-644 LVDS Standard
o Single +3.3V Supply
o Fail-Safe Circuit
____________________________Features
Pin Configuration appears at end of data sheet.
LVTTL/LVCMOS
DATA INPUT
Resistors (MAX9122)
MAX9121EUE
MAX9122EUE
MAX9121ESE
MAX9122ESE
Simplifies PC Board Layout
Reduces Crosstalk
PART
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
MAX9123
T
T
T
T
Typical Application Circuit
X
X
X
X
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Ordering Information
LVDS SIGNALS
107Ω
107Ω
107Ω
107Ω
MAX9122
R
R
R
R
X
X
X
X
PIN-PACKAGE
16 TSSOP
16 SO
16 TSSOP
16 SO
LVTTL/LVCMOS
DATA OUTPUT
1

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MAX9122 Summary of contents

Page 1

... LVDS standard. Flow-through pinout simplifies PC board layout and reduces crosstalk by separating the LVDS inputs and LVCMOS outputs. The MAX9121/ MAX9122 operate from a single +3.3V supply, and are specified for operation from -40°C to +85°C. These devices are available in 16-pin TSSOP and SO packages. ...

Page 2

... 3. Figure 1 IN2 3. Figure 1 DIFF CC Open, undriven short, or undriven 100Ω parallel I = -4.0mA OH termination (MAX9121 +100mV ID Open or undriven short I = -4.0mA OH (MAX9122 +100mV +4.0mA -100mV Enabled 0.1V (Note OUT I Disabled OUT / ...

Page 3

... Differential Part-to-Part Skew (Note 8) Rise-Time Fall-Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency (Note 9) _______________________________________________________________________________________ Quad LVDS Line Receivers with | = 0.1V to 1.0V, common-mode voltage +3.3V +25°C, unless otherwise noted.) (Note 1) ...

Page 4

... CC Note the magnitude difference of any differential propagation delays between parts operating over rated conditions. SKD4 Note 9: f generator output conditions: rise-time = fall-time = 1ns (0% to 100%), 50% duty cycle, V MAX MAX9121/MAX9122 output criteria: 60% to 40% duty cycle +3.3V +1.2V 0.2V SUPPLY CURRENT vs ...

Page 5

Integrated Termination and Flow-Through Pinout (V = +3.3V +1.2V 0.2V OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE 100 3.0 3.3 SUPPLY VOLTAGE (V) DIFFERENTIAL ...

Page 6

... The internal termination saves board space, eases lay- out, and reduces stub length compared to an external termination resistor. In other words, the transmission line is terminated on the IC. The fail-safe feature of the MAX9121/MAX9122 sets an output high when: • Inputs are open. • Inputs are undriven and shorted. ...

Page 7

... R IN1 IN_- close to the device as possible, with the smaller valued capacitor closest to V Input trace characteristics affect the performance of the MAX9121/MAX9122. Use controlled-impedance PC - 0.3V CC board traces to match the cable characteristic imped- ance. The termination resistor is also matched to this characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together ...

Page 8

... EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. The MAX9122 has an integrated termination resistor connected across the inputs of each receiver. The 8 _______________________________________________________________________________________ IN_+ ...

Page 9

... OUTPUT WHEN V = +100mV ID Figure 5. High-Impedance Delay Waveforms Because the MAX9121/MAX9122 feature a flow-through pinout, no special layout precautions are required. Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. For LVDS applications, a four-layer PC board that pro- vides separate power, ground, LVDS signals, and input signals is recommended ...

Page 10

... IN4 MAX9121 GND IN1 IN1 OUT1 IN2 OUT2 MAX9121 IN2 MAX9122 IN3 GND IN3 OUT3 IN4 OUT4 IN4 TSSOP/SO Functional Diagram V CC OUT1 OUT2 OUT3 OUT4 MAX9122 GND Pin Configuration ...

Page 11

Integrated Termination and Flow-Through Pinout ______________________________________________________________________________________ Quad LVDS Line Receivers with Package Information 11 ...

Page 12

... Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...

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