MAX9129 Maxim, MAX9129 Datasheet - Page 8

• Manufacturer Part Number: MAX9129
• Description: The MAX9129 is a quad bus low-voltage differential signaling (BLVDS) driver with flow-through pinout
• Manufacturer: Maxim

The reduction in characteristic impedance is approxi-
mated by the following formula:
where:
Z
pedance
C
C
N = number of capacitive loads
L = trace length
For example, if C
18in, and Z
impedance is:
In this example, capacitive loading reduces the charac-
teristic impedance from 120Ω to 54Ω. The load seen by
a driver located on a card in the middle of the bus is
27Ω because the driver sees two 54Ω loads in parallel.
A typical LVDS driver (rated for a 100Ω load) would not
develop a large enough differential signal to be reliably
detected by an LVDS receiver. Maxim’s BLVDS driver is
designed and specified to drive a 27Ω load to differen-
tial voltage levels of 250mV to 450mV (which are stan-
dard LVDS driver levels). A standard LVDS receiver is
able to detect this level of differential signal.
Short extensions off the bus, called stubs, contribute to
capacitive loading. Keep stubs less than 1in for a good
balance between ease of component placement and
good signal integrity.
The MAX9129 is a current source driver and drives
larger differential signal levels into loads higher than
27Ω and smaller levels into loads less than 27Ω (see
typical operating curves). To keep loading from reduc-
ing bus impedance below the rated 27Ω load, PC
board traces can be designed for higher unloaded
characteristic impedance.
For transition times (measured from 0% to 100%) short-
er than the delay between capacitive loads, the loads
are seen as low-impedance discontinuities from which
the driven signal is reflected. Reflections add and sub-
tract from the signal being driven and cause decreased
noise margin and jitter. The MAX9129 is designed for a
Quad Bus LVDS Driver with
Flow-Through Pinout
8
Z
C
DIFF-unloaded
o
L
DIFF-loaded
L
= unloaded trace capacitance (pF/unit length)
= value of each capacitive load (pF)
_______________________________________________________________________________________
/ L)]
Z
(2.5pF + 18
DIFF-loaded
DIFF-unloaded
= Z
= unloaded differential characteristic im-
DIFF-unloaded
o
Z
= 2.5pF/in, C
DIFF-loaded
✕
= 120Ω
10pF/18in)]
Effect of Transition Time
= 120Ω, the loaded differential
✕
✕
= 54Ω
SQRT [2.5pF /
L
SQRT [C
= 10pF, N = 18, L =
o
/ (C
o
+ N
✕
minimum transition time of 1ns (rated 0.6ns from 20% to
80%, or about 1ns 0% to 100%) to reduce reflections
while being fast enough for high-speed backplane data
transmission.
The power-on reset voltage of the MAX9129 is typically
2.25V. When the supply falls below this voltage, the
device is disabled and the outputs are in high imped-
ance.
Bypass V
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to V
In the example above, the loaded differential imped-
ance of the bus is reduced to 54Ω. Since it can be dri-
ven from any card position, the bus must be terminated
at each end. A parallel termination of 54Ω at each end
of the bus placed across the traces that make up the
differential pair provides a proper termination. The total
load seen by the driver is 27Ω.
The MAX9129 drives higher differential signal levels
into lighter loads. A multidrop bus with the driver at one
end and receivers connected at regular intervals along
the bus has a lowered impedance due to capacitive
loading. Assuming the same impedance calculated in
the multidrop example above (54Ω), the multidrop bus
can be terminated with a single, parallel-connected
54Ω resistor at the far end from the driver. Only a single
resistor is required because the driver sees one 54Ω
differential trace. The signal swing is larger with a 54Ω
load.
In general, parallel terminate each end of the bus with a
resistor matching the differential impedance of the bus
(taking into account any reduced impedance due to
loading).
A four-layer PC board that provides separate power,
ground, input, and output signals is recommended.
Keep the LVTTL/LVCMOS and BLVDS signals separat-
ed to prevent coupling as shown in the suggested lay-
out for the QFN package (not drawn to scale) (Figure 6).
CC
with high-frequency, surface-mount
Applications Information
CC
Power-Supply Bypassing
.
Power-On Reset
Board Layout
Termination