MAX9224 Maxim, MAX9224 Datasheet

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MAX9224

Manufacturer Part Number
MAX9224
Description
The MAX9223/MAX9224 serializer/deserializer chipsets reduce wiring by serializing 22 bits onto a single differential pair
Manufacturer
Maxim
Datasheet
The MAX9223/MAX9224 serializer/deserializer chipsets
reduce wiring by serializing 22 bits onto a single differen-
tial pair. 22 bits are serialized in each cycle of the paral-
lel input clock resulting in a 110Mbps to 220Mbps net
serial-data rate ideal for cell phone QVGA and QCIF dis-
plays. The MAX9223 serializes the 18-bit RGB, VSYNC,
HSYNC, and two control signals from the baseband
processor to reduce wiring through the hinge to the LCD
controller. The 2-wire serial interface uses low-current dif-
ferential signaling (LCDS) for low EMI, high common-
mode noise immunity, and ground-shift tolerance. The
MAX9223/MAX9224 automatically identify the word
boundary in serial data in case of signal interruption. The
MAX9224 power-down is controlled by the MAX9223.
The MAX9223 and MAX9224 consume 3.5µA or less in
power-down mode.
The MAX9223 serializer operates from a single +2.375V
to +3.465V supply and accepts +1.71V to +3.465V
inputs. The MAX9224 deserializer operates from a
+2.375V to +3.465V core supply and has a separate
output buffer supply (V
+3.465V output high levels.
The MAX9223/MAX9224 are specified over the -40°C to
+85°C extended temperature range and are available
in 28-pin TQFN (4mm x 4mm x 0.8mm) packages with
an exposed paddle.
19-3861; Rev 1; 12/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Cell Phones
LCDs
Digital Cameras
PARALLEL
CLOCK IN
DATA IN
PIXEL
MAX9223
________________________________________________________________ Maxim Integrated Products
General Description
LATCH
INPUT
DDO
Serializer and Deserializer Chipsets
), allowing +1.71V to
22-Bit, Low-Power, 5MHz to 10MHz
CONTROL
TIMING
AND
DLL
Applications
POWER-DOWN
CONTROL
LCDS
♦ Ideal for Serializing Cell Phone LCD or Imager
♦ MAX9223 Serializes 18-Bit RGB, VSYNC, HSYNC,
♦ LCDS Rejects Common-Mode Noise
♦ Automatic Location of Word Boundary After Signal
♦ Power-Down Control Through the Serial Link
♦ Power-Down Supply Current
♦ +2.375V to +3.465V Core Supply Voltage
♦ Parallel I/O Interfaces Directly to 1.8V to 3.3V Logic
♦ ±15kV Human Body Model ESD Protection
♦ -40°C to +85°C Operating Temperature Range
Pin Configurations appear at end of data sheet.
+Denotes lead-free package.
*EP = Exposed paddle.
MAX9223ETI
MAX9223ETI+
MAX9224ETI
MAX9224ETI+
Parallel Interface
and Two Control Signals
Interruption
MAX9224
PART
0.5µA (max)—MAX9223
3.0µA (max)—MAX9224
Typical Application Circuit
TIMING AND CONTROL
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
TEMP RANGE
Ordering Information
PIN-
PACKAGE
28 TQFN-EP*
28 TQFN-EP*
28 TQFN-EP*
28 TQFN-EP*
PIXEL
CLOCK OUT
PARALLEL
DATA OUT
Features
PKG
CODE
T2844-1
T2844-1
T2844-1
T2844-1
1

Related parts for MAX9224

MAX9224 Summary of contents

Page 1

... The MAX9223/MAX9224 automatically identify the word boundary in serial data in case of signal interruption. The MAX9224 power-down is controlled by the MAX9223. The MAX9223 and MAX9224 consume 3.5µA or less in power-down mode. The MAX9223 serializer operates from a single +2.375V to +3.465V supply and accepts +1.71V to +3.465V inputs ...

Page 2

... Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS— ...

Page 3

... PCLKOUT = 5MHz C = 5pF (110Mbps 2.5V, I TOTW DDO PCLKOUT = 10MHz Figure 2 (220Mbps) I TOTZ V MAX9223 V to MAX9224 MAX9223 to MAX9224 ground difference GD MIN TYP MAX = -1mA 0 DDO = 1mA 0 2.375V -2 = 3.135V -9 = 3.465V -25 400 -300 ±500 +300 69 90 109 ...

Page 4

... DD A PARAMETER SYMBOL PCLKIN INPUT REQUIREMENTS (Figure 3) Input Rise Time Input Fall Time PCLKIN Period High-Level Pulse Width Low-Level Pulse Width Setup Time Hold Time AC ELECTRICAL CHARACTERISTICS—MAX9224 ( +2.375V to +3.465V DDO L +2.5V +25°C.) (Notes PARAMETER SYMBOL PCLKOUT Period ...

Page 5

... Figure 2. Deserializer Worst-Case Switching Pattern PWL PWL THE MAXIMUM LOW-LEVEL OUTPUT (SEE THE DC ELECTRICAL CHARACTERISTICS TABLE). OL Test Circuits/Timing Diagrams t PWH PWH ...

Page 6

... PCLKIN = 10MHz 6 4 PCLKIN = 5MHz 2 3.5 2.3 2.5 2.7 2.9 3.1 SUPPLY VOLTAGE (V) MAX9223 SUPPLY CURRENT vs. FREQUENCY 8 DIN[21:0] = WORST-CASE SWITCHING PATTERN FREQUENCY (MHz) MAX9224 SUPPLY CURRENT vs. SUPPLY VOLTAGE 12 DOUT[21:0] = ALL HIGH PCLKOUT = 10MHz PCLKOUT = 5MHz 8 7 3.5 2.3 2.5 2.7 2.9 3.1 SUPPLY VOLTAGE (V) 3.3 3 3.3 3.5 ...

Page 7

... SINK CURRENT (mA) = +25°C, unless otherwise noted.) A MAX9224 SUPPLY CURRENT vs. FREQUENCY 12 DOUT[21:0] = ALL HIGH 2. FREQUENCY (MHz) MAX9224 DOUT OUTPUT-HIGH VOLTAGE vs. SOURCE CURRENT 2. DDO DDO 2.50 2.25 2.00 1.75 1. 1.71V DDO 1.25 3.3 3.5 0 0.2 0.4 0.6 SOURCE CURRENT (mA) MAX9224 DIFFERENTIAL INPUT 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE ( ...

Page 8

... Parallel Clock Input. The rising edge of PCLKIN (typically the pixel clock) latches the parallel 13 PCLKIN data input. Internally pulled down to GND. Power-Down Input. Pull PWRDN low to place the MAX9223 and MAX9224 in power-down mode. PWRDN 16 Drive PWRDN high for normal operation. Internally pulled down to GND. ...

Page 9

... PCLKOUT. The first bit (G) is internally grounded and transmitted first. Bit 0 (DIN[0]) is the first valid data bit. Boundary bits OH are used by the MAX9224 deserializer to identi- fy the word boundary and are the inverse polarity of data bit 21 (DIN[21]). Therefore, at least one level tran- sition is guaranteed in one word ...

Page 10

... PCLKOUT. Figure 4 shows the deserializer output timing. Power-Down and Power-Up Driving PWRDN low puts the MAX9223 in power-down mode and sends a pulse to power down the MAX9224. In power-down mode, the DLL is stopped, SDO+/SDO- are high impedance to ground and differential, and the LCDS - 0.8V. With PWRDN ...

Page 11

... The MAX9223/MAX9224 LCDS inputs and outputs (SDO+/SDO-, SDI+/SDI-) are rated for ±15kV ESD pro- tection using the Human Body Model. The Human Body Model discharge components are C 1.5kΩ ...

Page 12

... DIN1 DOUT14 22 PCLKIN 13 DOUT15 23 12 DIN2 DOUT16 24 DIN3 11 25 DOUT17 10 26 DIN4 DOUT18 DIN5 9 DOUT19 27 8 DIN6 DOUT20 Pin Configurations DOUT6 13 DOUT5 12 DOUT4 DOUT3 11 MAX9224 10 DOUT2 PCLKOUT 9 8 DOUT1 TQFN-EP ...

Page 13

... Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) ______________________________________________________________________________________ Package Information 13 ...

Page 14

... Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 14 ______________________________________________________________________________________ Package Information (continued) ...

Page 15

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © ...

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