MAX9254 Maxim, MAX9254 Datasheet
MAX9254
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MAX9254 Summary of contents
Page 1
... LVDS clock input and scales linearly with frequency. The single-ended outputs have a sepa- rate supply, allowing +1.8V to +5V output logic levels. The MAX9254 features high output drive current for both data and clock outputs for faster transition times in the presence of heavy capacitive loads. ...
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... L Non-DC-balanced worst-case pattern, mode (SSG = low 3.0V CC CCO to 3.6V, Figure anced (MAX9242 en) 34MHz MAX9244, MAX9254 anced m ode ( en) 40MHz = 330Ω 150pF 2.0kΩ 330pF 2. 2|, unless otherwise ...
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... 2.5 0.3 -10 +10 -0.3 +0.8 -20 +20 -1.5 V CCO - 0.1 V CCO - 0.25 V CCO - 0.43 V CCO MAX9254 - 0.25 0.1 0.2 0.26 MAX9254 0.2 UNITS mA µ µ µA V µ ...
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... Typical values are PARAMETER SYMBOL Output Rise Time CLHT Output Fall Time CHLT Output Rise Time (MAX9254) CLHT Output Fall Time (MAX9254) CHLT RxIN__ Skew Margin (Note 9) RSKM 4 _______________________________________________________________________________________ = +3.0V to +5.5V, PWRDWN = high; SSG = high, open, or low; DCB = high or CCO = LVDSV = PLLV = +3 ...
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... V and Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested +25°C. A Note 3: To provide a mid level, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current must be less than ±10µA. ...
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Deserializers with Programmable Spread Spectrum and DC Balance FAIL-SAFE IN2 COMPARATOR RxIN_ + OR RxIN_ + OR RxCLKIN+ RxCLKIN 0. IN1 IN1 R R IN1 IN1 RxIN_ - OR RxIN_ - ...
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... Figure 6b. Clock-IN to Clock-OUT Delay (MAX9242) PWRDWN 1.5V RxCLKIN_ RPDD RxOUT_ RxCLKOUT Figure 8. Power-Down Delay _______________________________________________________________________________________ Test Circuits/Timing Diagrams (continued) RxCLKIN_ 0.8V 0.8V RCOL RHRC 2.0V 0.8V Figure 6a. Clock-IN to Clock-OUT Delay (MAX9244/MAX9246/ MAX9254) PWRDWN V CC RxCLKIN_ RxCLKOUT Figure 7. Phase-Locked-Loop Set Time 1.5V HIGH IMPEDANCE RCIP RCCD 1.5V RxCLKOUT 2V 3V RPLLS 1 ...
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... Deserializers with Programmable Spread Spectrum and DC Balance SSG RxCLKIN_ RxCLKOUT RxOUT_ TIMING SHOWN FOR FALLING-EDGE STROBE (MAX9244/MAX9246/MAX9254) PWRDWN = HIGH Figure 9. Phase-Locked-Loop Set Time from SSG Change FREQUENCY SSM f (MAX) RxCLKOUT f RxCLKIN_ f (MIN) RxCLKOUT Figure 10. Simplified Modulation Profile 8 _______________________________________________________________________________________ Test Circuits/Timing Diagrams (continued) 2.5V OPEN OR LESS THAN ± ...
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... Deserializers with Programmable Spread Spectrum and DC Balance (V = PLLV = LVDSV = V = +3.3V CCO voltage V = 1.2V +25°C, MAX9244/MAX9254, unless otherwise noted WORST-CASE AND PRBS SUPPLY CURRENT vs. FREQUENCY (NON-DC-BALANCED MODE, NO SPREAD) 100 90 WORST-CASE PATTERN PRBS ...
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... Deserializers with Programmable Spread Spectrum and DC Balance (V = PLLV = LVDSV = V = +3.3V CCO voltage V = 1.2V +25°C, MAX9244/MAX9254, unless otherwise noted RxCLKOUT POWER SPECTRUM vs. FREQUENCY (RxCLKIN_ = 16MHz, NO SPREAD -10 -20 -30 -40 -50 -60 RESOLUTION BW = 100kHz VIDEO BW = 100kHz -70 ATTENUATION = 50dB - FREQUENCY (MHz) RxOUT_ POWER SPECTRUM vs ...
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Deserializers with Programmable Spread Spectrum and DC Balance PIN NAME 1 RxOUT17 Channel 2 Single-Ended Outputs 2 RxOUT18 3, 25, 32, GND Ground 38 RxOUT19 Channel 2 Single-Ended Outputs 5 RxOUT20 Three-Level-Logic, Spread-Spectrum Generator Control Input. SSG ...
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... CHANNEL 1 7 SERIAL-TO-PARALLEL FIFO CHANNEL 2 7 SERIAL-TO-PARALLEL PARALLEL STROBES CLK CLK CLOCK IN OUT PLL1 FIFO CONTROL MAX9242 SPREAD- MAX9244 SPECTRUM MAX9246 PLL (SSPLL) MAX9254 SSG PWRDWN Pin Description (continued) Functional Diagram 7 RxOUT0–RxOUT6 7 RxOUT7–RxOUT13 7 RxOUT14–RxOUT20 RxCLKOUT ...
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... MOS/LVTTL outputs. The outputs are programmable for no spread or for a spread of ±2% or ±4%, relative to the LVDS input clock frequency. The MAX9242/MAX9244/ MAX9254 operate at a parallel clock frequency of 16MHz to 34MHz in DC-balanced mode and 20MHz to 40MHz in non-DC-balanced mode. The MAX9246 operates at a 6MHz-to-18MHz parallel clock frequency in DC-balanced mode and 8MHz-to-20MHz parallel clock frequency in non-DC-balanced mode ...
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... The PLL control voltage does not saturate in response to high-frequency glitches that may occur during a hot swap. The PWRDWN input on the MAX9242/MAX9244/MAX9246/ MAX9254 does not need to be cycled when these devices FUNCTION are connected to an active serializer. The MAX9242/MAX9244/MAX9246/MAX9254 use two PLLs ...
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Deserializers with Programmable Spread Spectrum and DC Balance ±4% OR ±2% SPREAD SSG RxCLKOUT RxOUT_ Figure 13. Output Waveforms when Spread Amount is Changed SSG NO SPREAD RxCLKOUT RxOUT_ Figure 14. Output Waveforms when Spread is Added ±4% OR ...
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Deserializers with Programmable Spread Spectrum and DC Balance INTERNAL PLL1 LOCK INTERNAL SSPLL LOCK RxCLKOUT RxOUT_ Figure 16. Output Waveforms when PLL1 Loses Lock and Locks Again INTERNAL SSPLL LOCK RxCLKOUT RxOUT_ TIMING SHOWN FOR STABLE CLOCK AND DATA ...
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... transition time ( 100 droop (% of signal amplitude) Jitter due to 2% droop and assumed 1ns transition time is: The transition time in a real system depends on the fre- quency response of the cable driven by the serializer. MAX9242/MAX9244/MAX9246/MAX9254 7 1:7 FIFO 7 1:7 FIFO RxOUT_ 7 1:7 FIFO PWRDWN ...
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... Equation 1 altered for four series capacitors (Figure 20 DSV The MAX9242/MAX9244/MAX9246/MAX9254 have fail- safe LVDS inputs in non-DC-balanced mode (Figure 1). Fail-safe drives the outputs low when the corresponding LVDS input is open, undriven and shorted, or undriven and parallel terminated. The fail-safe on the LVDS clock input drives all outputs low when power is stable ...
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... A four-layer PC board with separate layers for power, ground, LVDS inputs, and digital signals is recommended. Layout PC board traces for 100Ω differential characteristic imped- with high-frequency, ance. The trace dimensions depend on the type of MAX9242/MAX9244/MAX9246/MAX9254 7 1:( FIFO 7 1:( RxOUT_ ...
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... The MAX9242 has a rising-edge output strobe, which latches the parallel output data into the next chip on the rising edge of RxCLKOUT. The MAX9244/MAX9246/ MAX9254 have a falling-edge output strobe, which latches the parallel output data into the next chip on the falling edge of RxCLKOUT. The deserializer output strobe polarity does not need to match the serializer input strobe polarity ...
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... ISO 10605. The ISO 10605 and IEC 61000-4-2 standards specify ESD tolerance for electronic sys- tems. All LVDS inputs on the MAX9242/MAX9244/ MAX9246/MAX9254 meet ISO 10605 ESD protection at ±30kV Air-Gap Discharge and ±6kV Contact Discharge and IEC 61000-4-2 ESD protection at ±15kV Air-Gap Discharge and ± ...
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... MAX9246GUM -40°C to +105°C MAX9246GUM/V+ -40°C to +105°C MAX9254EUM -40°C to +85°C MAX9254EUM/V+ -40°C to +85°C + Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. Note: All devices are available in lead(Pb)-free/RoHS-compliant packaging. Specify lead(Pb)-free/RoHS compliant by adding a + symbol at the end of the part number when ordering. ...
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... Added automotive qualified parts to Ordering Information table Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...