MAX9248 Maxim, MAX9248 Datasheet
MAX9248
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MAX9248 Summary of contents
Page 1
... Proprietary data decoding reduces EMI and provides DC balance. The DC balance allows AC-coupling, pro- viding isolation between the transmitting and receiving ends of the interface. The MAX9248/MAX9250 feature a selectable rising or falling output latch edge. ESD tolerance is specified for ISO 10605 with ±10kV Contact Discharge and ±30kV Air-Gap Discharge. ...
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... LQFP (derate 21.7mW/°C above +70°C).....1739mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... MAX9250 RNG1 = low C = 8pF, L RNG0 = high worst-case RNG1 = high pattern, RNG0 = low Figure 2 RNG1 = high RNG0 = high RNG1 = low RNG0 = low RNG1 = low MAX9248 RNG0 = high C = 8pF, L worst-case RNG1 = high pattern, RNG0 = low Figure 2 RNG1 = high RNG0 = high I (Note 4) CCZ CM = +3.3V, ⏐V ⏐ ...
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... Figure 3 R MAX9250ECM RNG1 = low MAX9248/ MAX9250GCM t Figure 4 HIGH t Figure 4 LOW t Figure 5 DVB t Figure 5 DVA MAX9248, Figure 8 PLLREF MAX9250, Figure 7 Maximum output frequency SS = high, Figure 11 Minimum output frequency Maximum output frequency SS = low, Figure 11 Minimum output frequency ⏐ = 0.1V to 1.2V, input common-mode voltage ID = +3.3V, ⏐V ...
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... Note 4: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ V Note 5: C includes probe and test jig capacitance. L _______________________________________________________________________________________ 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers CONDITIONS f Figure 11 SSM t Figures 7, 8 PDD MAX9248, Figure 17 ΔSSPLL t MAX9250, Figure MAX9250, Figure 0.3V. PWRDWN is ≤ 0.3V, REFCLK is static. CC ⏐ = 0.1V to 1.2V, input common-mode voltage ID = +3.3V, ⏐V CC_ ...
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... DC-Balanced LVDS Deserializers ( +3.3V 8pF +25°C, unless otherwise noted WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY MAX9248 MAX9250 FREQUENCY (MHz) OUTPUT POWER SPECTRUM vs. FREQUENCY (REFCLK = 42MHz, NO SPREAD, 4%, AND 2% SPREAD) 0 RESOLUTION BW = 30kHz ...
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... PIN NAME MAX9248 MAX9250 RNG1 CCLVDS LVDSGND 7 7 PLLGND CCPLL 9 9 RNG0 10 10 GND REFCLK PWRDWN — SS CNTL_OUT0– 15–23 15–23 CNTL_OUT8 24 24 DE_OUT 25 CCOGND 26, 38 26, 38 ...
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... DC-Balanced LVDS Deserializers PIN NAME MAX9248 MAX9250 LOCK PCLK_OUT RGB_OUT0– 29–36, 29–36, RBG_OUT7, 39–48 39–48 RGB_OUT8– RGB_OUT17 — 14 OUTEN IN IN- REFCLK PLL SSPLL TIMING AND CONTROL RNG[0:1] 8 _______________________________________________________________________________________ LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low. ...
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IN 1. IN- Figure 1. LVDS Input Bias 0 CCO DE_OUT LOCK PCLK_OUT 0 CCO RGB_OUT[17: CNTL_OUT[8:0] Figure 3. Output Rise and Fall Times PCLK_OUT PCLK_OUT SHOWN FOR R/F = ...
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... Figure 7. PLL Lock to REFCLK and Power-Down Delay for MAX9250 0.8V PWRDWN REFCLK HIGH IMPEDANCE PCLK_OUT RGB_OUT CNTL_OUT HIGH IMPEDANCE DE_OUT HIGH IMPEDANCE LOCK NOTE: R/F = HIGH Figure 8. PLL Lock to REFCLK and Power-Down Delay for MAX9248 10 ______________________________________________________________________________________ 0.8V TRANSITION t PLLREF WORD FOUND CLOCK STRETCH TRANSITION t PLLREF ...
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OUTEN 0. DE_OUT RGB_OUT[17:0] HIGH IMPEDANCE CNTL_OUT[8:0] Figure 9. Output Enable Time FREQUENCY SSM f (MAX) RxCLKOUT f RxCLKIN f (MIN) RxCLKOUT Figure 11. Simplified Modulation Profile ______________________________________________________________________________________ 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers ...
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... RGB_OUT[17:0] out- puts when the data-enable output DE_OUT is high, or control data to the CNTL_OUT[8:0] outputs when DE_OUT is low. The outputs on the MAX9248 are pro- grammable for ±2% or ±4% spread relative to the LVDS input clock frequency, while the MAX9250 has no spread, but has an output-enable input that allows out- put busing ...
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RGB_IN 1 0 CNTL_IN DE_IN PCLK_IN TIMING AND RNG0 PLL CONTROL RNG1 PWRDWN MAX9247 CERAMIC RF SURFACE-MOUNT CAPACITOR Figure 12. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Two Capacitors per Link RGB_IN 1 0 CNTL_IN DE_IN PCLK_IN TIMING AND RNG0 ...
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... DE_IN PCLK_IN TIMING AND RNG0 PLL CONTROL RNG1 PWRDWN MAX9247 CERAMIC RF SURFACE-MOUNT CAPACITOR *CAPACITORS CAN BE AT EITHER END. Figure 14. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Two Capacitors per Link RGB_IN 1 0 CNTL_IN DE_IN PCLK_IN TIMING AND RNG0 PLL CONTROL RNG1 ...
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... PCLK_OUT are driven low. REFCLK is output on PCLK_OUT and the deserializer continues monitoring the serial input for a transition word. See Figure 7 for the MAX9250 and Figure 8 for the MAX9248 regarding the synchronization timing diagram. The MAX9248 input-to-output delay can be as low as (4 ...
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... DC-Balanced LVDS Deserializers Spread-Spectrum Selection The MAX9248 single-ended data and clock outputs are programmable for a variation of ±2% or ±4% around the LVDS input clock frequency. The modulation rate of the frequency variation is 32kHz for a 33MHz LVDS clock input and scales linearly with the clock frequency (see Table 4) ...
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... MAX9248/MAX9250 Video Link The MAX9247 and MAX9248/MAX9250 video link can be powered up in several ways. The best approach is to keep both MAX9247 and MAX9248 powered down while supplies are ramping up and PCLK_IN of the MAX9247 and REFCLK of the MAX9248/MAX9250 are stabilizing. After all of the power supplies of the ...
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... Human Body Model, Machine Model, IEC 61000-4-2 and ISO 10605. The ISO 10605 and IEC 61000-4-2 standards specify ESD tolerance for electronic systems. All LVDS inputs on the MAX9248/MAX9250 meet ISO 10605 ESD protection at ±30kV Air-Gap Discharge and ±10kV Contact Discharge and IEC 61000-4-2 ESD protection at ± ...
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... Chip Information PROCESS: CMOS ______________________________________________________________________________________ 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE 48 LQFP Package Information PACKAGE CODE DOCUMENT NO. C48+3 21-0054 19 ...
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... uenci 9247 and M AX 9248/M AX 9250 secti on Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...