MAX9405 Maxim, MAX9405 Datasheet
MAX9405
Related parts for MAX9405
MAX9405 Summary of contents
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... The MAX9402 has open inputs and 50Ω series outputs. The MAX9403 has 100Ω differential input impedance and open emitter outputs. The MAX9405 has 100Ω differential input impedance and 50Ω series outputs. These devices operate with a supply voltage ...
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... MAX9400/ CLK, or CLK = V MAX9402 , I IL EN, EN, SEL, SEL, CLK, or MAX9403/ CLK = V MAX9405 or V IHD R MAX9403/MAX9405 Figure 1 OL Figure 1 OCM MAX9402/MAX9405, Figure 2 SINK MAX9402/MAX9405, Figure 2 OUT MAX9402/MAX9405 I EE MAX9400/MAX9403 - 2.0V. Typical values are MIN TYP MAX 1 ...
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... IHD CC CONDITIONS MAX9400/MAX9403 t PLH1 SEL = high, Figure 3 t MAX9402/MAX9405 PHL1 MAX9400/MAX9403 t PLH2 SEL = low, Figure 4 t MAX9402/MAX9405 PHL2 t SEL = high SKD1 t SEL = low SKD2 ≥ 500mV, SEL = low ≥ 400mV, SEL = high IN(MAX SEL = low ...
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Quad Differential LVECL/LVPECL Buffer/Receivers ( 3.3V, MAX9400, outputs terminated with 50Ω ± input transition time = 125ps (20% to 80%), V SUPPLY CURRENT ( vs. TEMPERATURE ...
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PIN NAME 1, 8,11, Positive Supply Voltage. Bypass 17, 24, 30 capacitors as close to the device as possible with the smaller value capacitor closest to the device. Noninverting Differential Select Input. Setting SEL = high and ...
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... The MAX9403/MAX9405 have inte- grated 100Ω differential input termination resistors from IN_ to IN_, reducing external component count. The MAX9402/MAX9405 have internal 50Ω series out- put termination resistors and 8mA internal pulldown current sources. Using integrated resistors reduces external component count. ...
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... IHD (MAX) ILD (MIN) IHD (MIN) ILD OUTPUT VOLTAGE DEFINITION MAX9403/MAX9405 V CC OUT_ 8mA OUT_ MAX9402/MAX9405 Buffer/Receivers Chip Information OCM IN_ 100Ω IN_ V CC 50Ω OUT_ 50Ω OUT_ 8mA ...
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Quad Differential LVECL/LVPECL Buffer/Receivers IN_ IN_ OUT_ OUT_ DIFFERENTIAL OUTPUT WAVEFORM OUT_ - OUT_ Figure 3. IN-to-OUT Propagation Delay and Transition Timing Diagram CLK CLK t H IN_ IN_ OUT_ OUT_ Figure 4. CLK-to-OUT Propagation Delay Timing Diagram 8 _______________________________________________________________________________________ ...
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... QFN-EP* *EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO V _______________________________________________________________________________________ Quad Differential LVECL/LVPECL V CC IN_ OUT_ OUT_ IN_ 1kΩ OUT1 22 OUT1 OUT2 18 OUT2 Buffer/Receivers V CC OUT_ 100Ω OUT_ 1/4 MAX9403/MAX9405 ...
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Quad Differential LVECL/LVPECL Buffer/Receivers IN0 IN0 IN1 IN1 IN2 IN2 IN3 IN3 CLK CLK SEL SEL ______________________________________________________________________________________ ...
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... For the latest package outline information www.maxim-ic.com/packages.) ______________________________________________________________________________________ Quad Differential LVECL/LVPECL Buffer/Receivers Package Information PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm 1 B 21-0110 2 PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm ...
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... Quad Differential LVECL/LVPECL Buffer/Receivers (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages. 12 ______________________________________________________________________________________ Package Information (continued) ...
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... For the latest package outline information www.maxim-ic.com/packages. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...