74F244PC Fairchild Semiconductor, 74F244PC Datasheet

IC BUFF/DVR TRI-ST DUAL 20DIP

74F244PC

Manufacturer Part Number
74F244PC
Description
IC BUFF/DVR TRI-ST DUAL 20DIP
Manufacturer
Fairchild Semiconductor
Series
74Fr
Datasheets

Specifications of 74F244PC

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
4
Current - Output High, Low
3mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
74F244

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© 1999 Fairchild Semiconductor Corporation
74F240SC
74F240SJ
74F240PC
74F241SC
74F241SJ
74F241PC
74F244SC
74F244SJ
74F244MSA
74F244PC
74F240 • 74F241 • 74F244
Octal Buffers/Line Drivers with 3-STATE Outputs
General Description
The 74F240, 74F241 and 74F244 are octal buffers and line
drivers designed to be employed as memory and address
drivers, clock drivers and bus-oriented transmitters/receiv-
ers which provide improved PC and board density.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Order Code
Package Number
MSA20
M20B
M20D
M20B
M20D
M20B
M20D
N20A
N20A
N20A
74F240
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS009501
74F244
Features
3-STATE outputs drive bus lines or buffer memory
address registers
Outputs sink 64 mA (48 mA mil)
12 mA source current
Input clamp diodes limit high-speed termination effects
Package Description
74F241
April 1988
Revised July 1999
www.fairchildsemi.com

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74F244PC Summary of contents

Page 1

... Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F244MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74F244PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Logic Symbols IEEE/IEC 74F240 Unit Loading/Fan Out Pin Names Description 3-STATE Output Enable Input (Active LOW 3-STATE Output Enable Input (Active HIGH –I Inputs (74F240 –I Inputs (74F241, 74F244) ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 3) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...

Page 4

AC Electrical Characteristics Symbol Parameter t Propagation Delay PLH t Data to Output (74F240) PHL t Output Enable Time (74F240) PZH t PZL t Output Disable Time (74F240) PHZ t PLZ t Propagation Delay PLH t Data to Output (74F241, ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20B Package Number M20D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number MSA20 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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