IR3508ZMPBF International Rectifier, IR3508ZMPBF Datasheet - Page 8

• Manufacturer Part Number: IR3508ZMPBF
• Description: The IR3508ZM Phase IC combined with any IR XPhase3 Control IC provides a full featured and flexible way to implement a power solution for the latest high performance CPUs and ASICs.
• Manufacturer: International Rectifier

Specifications of IR3508ZMPBF

• Package: 20-Lead MLPQ
• Circuit: X-Phase Phase IC
• Pbf: PbF Option Available

Frequency and Phase Timing Control
The oscillator is located in the Control IC and the system clock frequency is programmable from 250kHz to 9MHZ by an
external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase
timing of the phase ICs is controlled by the daisy chain loop, where the control IC phase clock output (PHSOUT) is
connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to
PHSIN of the second phase IC, etc. The last phase IC is connected back to PHSIN of the control IC to complete the
daisy chain loop. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and
detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. When
the PSI is asserted (active low), the phases are effectively removed from the daisy chain loop. Figure 2 shows the
phase timing for a four phase converter. The switching frequency is set by the resistor ROSC. The clock frequency
equals the number of phase times the switching frequency.
PWM Operation
The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is set
and the PWM ramp voltage begins to increase. In addition, the low side driver is turned off and the high side driver is
turned on after the non-overlap time expires (GATEL < 1V). When the PWM ramp voltage exceeds the error amplifier’s
output voltage, the PWM latch is reset and the internal ramp capacitor is quickly discharged to the output of the share
adjust amplifier and remains discharged until the next clock pulse. This reset latch additionally turns off the high side
driver and enables the low side driver after the non-overlap time concludes (Switch Node < 1V).
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input
range, of the PWM comparator, results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees that the error amplifier is always in control and can demand 0 to 100% duty cycle as required.
It also favors response to a load step decrease, which is appropriate, given that the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response.” The inductor current will change in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in ground
or input voltage, at the phases, have no effect on operation since the PWM ramps are referenced to VDAC.
Figure 3 depicts PWM operating waveforms under various conditions.
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Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC1
PWM Latch SET
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
Figure 2: Four Phase Oscillator Waveforms
Jan 09, 2009
IR3508Z