IR3894MTR1PBF International Rectifier, IR3894MTR1PBF Datasheet
IR3894MTR1PBF
Specifications of IR3894MTR1PBF
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IR3894MTR1PBF Summary of contents
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FEATURES Single 5V to 21V application Wide Input Voltage Range from 1.0V to 21V with external Vcc Output Voltage Range: 0.5V to 0.86* Vin Enhanced Line/Load Regulation with Feed‐Forward Programmable Switching Frequency up to 1.5MHz Internal Digital Soft‐Start/Soft‐Stop Enable input with Voltage Monitoring Capability Thermally Compensated Current Limit with robust hiccup mode over current protection Smart internal LDO to improve light load and full load efficiency External Synchronization with Smooth Clocking Enhanced Pre‐Bias Start‐Up Precision Reference Voltage (0.5V+/‐0.5%) with margining capability Vp for Tracking Applications ((Source/Sink Capability +/‐12A) Integrated MOSFET drivers and Bootstrap Diode Thermal Shut Down Programmable Power Good Output with tracking capability ...
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... Single‐Input Voltage, Synchronous Buck Regulator Package M M Vref Comp Gnd Rt/SyncS_Ctrl PGood PCB - PD‐97745 IR3894 Tape & Reel Qty Part Number 750 IR3894MTR1PBF 4000 IR3894MTRPBF ...
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BLOCK DIAGRAM Figure 3: IR3894 Simplified Block Diagram 3 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator PD‐97745 IR3894 ...
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PIN DESCRIPTIONS PIN # PIN NAME 1 Fb 2 Vref 3 Comp 4 Gnd 5 Rt/Sync 6 S_Ctrl 7 PGood 8 Vsns 9 Vin 10 Vcc/LDO_Out 11 PGnd 12 SW 13 PVin 14 Boot 15 Enable 16 Vp 17 Gnd ...
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ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PVin, Vin Vcc/LDO_Out Boot SW Boot to SW S_Ctrl, PGood Other Input/Output Pins PGnd to Gnd Storage Temperature Range Junction Temperature Range ESD Classification Moisture Sensitivity Level Note 1: Must not exceed 8V Note 2: Vcc must not exceed 7.5V for Junction Temperature between ‐10°C and ‐40°C 5 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator ‐0.3V to 25V ‐0.3V to 8V (Note 2) ‐0.3V to 33V ‐0.3V to 25V (DC), ‐4V to 25V (AC, 100ns) ‐0.3V to Vcc + 0.3V (Note 1) ‐0.3V to Vcc + 0.3V (Note 1) ‐0.3V to +3.9V ‐0.3V to +0.3V ...
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ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN Input Voltage Range Input Voltage Range Supply Voltage Range Supply Voltage Range Output Voltage Range Output Current Range Switching Frequency Operating Junction Temperature *Maximum SW node voltage should not exceed 25V. ** Vcc/LDO_out can be connected to an external regulated supply. If so, the Vin input should be connected to Vcc/LDO_out pin. ELECTRICAL CHARACTERISTICS Unless otherwise specified, these specifications apply over, 6.8V < Vin = PVin < 21V, Vref = 0.5V in 0°C < T Typical values are specified at T = 25°C. a PARAMETER Power Stage Power Losses Top Switch Bottom Switch Bootstrap Diode Forward Voltage SW Leakage Current Dead Band Time Supply Current VIN Supply Current (standby) VIN Supply Current (dynamic) VCC LDO Output Output Voltage VCC Dropout Short Circuit Current Zero‐crossing Comparator Delay Zero‐crossing Comparator Offset 6 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator ...
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Single‐Input Voltage, Synchronous Buck Regulator PARAMETER Oscillator Rt Voltage Frequency Range Ramp Amplitude Ramp Offset Min Pulse Width Max Duty Cycle Fixed Off Time Sync Frequency Range Sync Pulse Duration Sync Level Threshold Error Amplifier Input Offset Voltage Input Bias Current Input Bias Current Sink Current Source Current Slew Rate Gain‐Bandwidth Product DC Gain Maximum output Voltage Minimum output Voltage Common Mode input Voltage Reference Voltage Feedback Voltage Accuracy 7 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck SYMBOL CONDITIONS ...
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Single‐Input Voltage, Synchronous Buck Regulator PARAMETER Vref Margining Voltage Sink Current Source Current Vref Comparator Threshold Soft Start/Stop Soft Start Ramp Rate Ramp(SS_start) Soft Start Ramp Rate Ramp(SS_stop) S_Ctrl Threshold Power Good Power Good Turn on Threshold Power Good Lower Turn off Threshold Power Good Turn on Delay Power Good Upper Turn off Threshold PGood Comparator Delay PGood Voltage Low Tracker Comparator Upper VPG(tracker_ Threshold Tracker Comparator Lower VPG(tracker_ Threshold Tracker Comparator Delay Tdelay(tracker) Vp Rising, Vref < 0.1V,see Under‐Voltage Lockout Vcc‐Start Threshold Vcc‐Stop Threshold Enable‐Start‐Threshold Enable_UVLO_ Enable‐Stop‐Threshold Enable_UVLO_ Enable Leakage Current ...
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PARAMETER Over‐Current Protection Current Limit Hiccup Blanking Time Over‐Temperature Protection Thermal Shutdown Threshold Hysteresis Note 3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. Note 4: Guaranteed by design but not tested in production. 9 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator SYMBOL CONDITIONS I Tj = 25°C, Vcc = 6.4V LIMIT Tblk_Hiccup Ttsd Note 4 Ttsd_hys Note 4 PD‐97745 IR3894 MIN TYP MAX UNIT 13.8 15.6 18.5 A ...
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TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vcc = Internal LDO (4.4V/6.4V), Io = 0A‐12A, Fs = 600kHz, Room Temperature, No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vout(V) Lout(µH) 1 1.2 1.8 3.3 5 ...
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TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vcc = External 5V, Io = 0A‐12A, Fs = 600kHz, Room Temperature, No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vout(V) Lout(µH) 1 1.2 1.8 3.3 5 ...
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TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 5.0V, Vcc = 5.0V, Io = 0A‐12A, Fs = 600kHz, Room Temperature, No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vout(V) Lout(µH) 1 0.4 1.2 0.4 1.8 0.51 3.3 0.51 ...
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THERMAL DERATING CURVES Measurement done on Evaluation board of IRDC3894.PCB is 4 layer board with 2 oz Copper, FR4 material, size 2.23"x2" PVin = 12V, Vout=1.2V, Vcc = Internal LDO (6.4V), Fs = 600kHz PVin = 12V, Vout=3.3V, Vcc = Internal LDO (6.4V), Fs = 600kHz 13 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator ...
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RDSON OF MOSFETS OVER TEMPERATURE AT V RDSON OF MOSFETS OVER TEMPERATURE AT V 14 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - ...
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TYPICAL OPERATING CHARACTERISTICS (‐40°C TO +125°C) 15 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator ...
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TYPICAL OPERATING CHARACTERISTICS (‐40°C TO +125°C) Note:See Over Current protection section Note:See Over Current Protection section 16 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator ...
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THEORY OF OPERATION DESCRIPTION The IR3894 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 300 KHz to 1.5MHz and provides the capability of optimizing the design in terms of size and performance. IR3894 provides precisely regulated output voltage programmed via two external resistors from 0.5V to 0.86*Vin. The IR3894 operates with an internal bias supply (LDO) which is connected to the Vcc/LDO_out pin. This allows operation with single supply. The bias voltage is variable according to load condition. If the output load current is less than half of the peak‐to‐peak inductor current, a lower bias voltage, 4.4V, is used as the internal gate drive voltage; otherwise, a higher voltage, 6.4V, is used. This feature helps the converter to reduce power losses. The IC can also be operated with an external supply from 4.5 to 7.5V, allowing an extended operating input voltage (PVin) range from 1.0V to 21V. For using the internal LDO supply, the Vin pin should be connected to PVin pin. If an external supply is used, it should be connected to Vcc/LDO_out pin and the Vin pin should be shorted to Vcc/LDO_out pin. The device utilizes the on‐resistance of the low side MOSFET (sync FET) as current sense element. This method enhances the converter’s efficiency and reduces cost by eliminating the need for external current sense resistor. IR3894 includes two low R MOSFETs using IR’s HEXFET ds(on) technology. These are specifically designed for high efficiency applications. UNDER‐VOLTAGE LOCKOUT AND POR The under‐voltage lockout circuit monitors the voltage of Vcc/Ldo pin and the Enable input. It assures that the ...
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Single‐Input Voltage, Synchronous Buck Regulator Pvin(12V) Enable >1.2V Intl_SS Figure 5a: Recommended startup for Normal operation Pvin (12V) Vcc Enable > Figure 5b: Recommended startup for sequencing operation (ratiometric or simultaneous) Pvin (12V) Vcc Vref=0 Enable > Figure 5c: Recommended startup for memory tracking operation (Vtt‐DDR) 18 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Figure 5a shows the recommended start‐up sequence for the normal (non‐tracking, non‐sequencing) operation of IR3894, when Enable is used as a logic input. In this operating mode Vref is left floating. Figure 5b shows the recommended startup sequence for sequenced operation Vcc ...
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SOFT‐START IR3894 has an internal digital soft‐start to control the output voltage rise and to limit the current surge at the start‐up. To ensure correct start‐up, the soft‐start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal soft‐start (Intl_SS) signal linearly rises with the rate of 0.2mV/µs from 0V to 1.5V. Figure 7 shows the waveforms during soft start (also refer to Fig. 20). The normal Vout start up time is fixed, and is equal to: 0.65V-0.15V T 2.5ms start 0.2mV/ s During the soft start the over‐current protection (OCP) and over‐voltage protection (OVP) is enabled to protect the device for any short circuit or over voltage condition. POR 1.5V 0.65V 0.15V Intl_SS Vout Figure 7: Theoretical operation waveforms during soft‐start (non tracking / non sequencing) OPERATING FREQUENCY The switching frequency can be programmed between 300 ...
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I (2) OCP LIMIT 2 I = DC current limit hiccup point OCP I = Current limit Valley Point LIMIT ΔI=Inductor ripple current Figure 8: Timing Diagram for Current Limit Hiccup THERMAL SHUTDOWN Temperature sensing is provided inside IR3894. The trip o threshold is typically set to 145 C. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and resets the internal soft start. Automatic restart is initiated when the sensed temperature drops within the operating range. There is o a 20 C hysteresis in the thermal shutdown threshold. EXTERNAL SYNCHRONIZATION ...
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Feed‐Forward Feed‐Forward (F.F.) is an important feature, because it can keep the converter stable and preserve its load transient performance when Vin varies in a large range. In IR3894, F.F. function is enabled when Vin pin is connected to PVin pin. In this case, the internal low dropout (LDO) regulator is used. The PWM ramp amplitude (Vramp) is proportionally changed with Vin to maintain Vin/Vramp almost constant throughout Vin variation range (as shown in Fig. 10). Thus, the control loop bandwidth and phase margin can be maintained constant. Feed‐forward function can also minimize impact on output voltage from fast Vin change. The maximum Vin slew rate is within 1V/µs. If an external bias voltage is used as Vcc, Vin pin should be connected to Vcc/LDO_out pin instead of PVin pin. Then the F.F. function is disabled. A re‐calculation of control loop parameters is needed for re‐compensation. Figure 10: Timing Diagram for Feed‐Forward (F.F.) Function SMART LOW DROPOUT REGULATOR (LDO) IR3894 has an integrated low dropout (LDO) regulator which can provide gate drive voltage for both drivers. In order to improve overall efficiency over the whole load range, LDO voltage is set to 6.4V (typical.) at mid‐ or heavy load condition to reduce Rds(on) and thus MOSFET conduction loss; and it is reduced to 4.4 (typical.) at light load condition to reduce gate drive loss. The smart LDO can select its output voltage according to the load condition by sensing switch node (SW) voltage. At light load condition when part of the inductor current flows in the reverse direction (DCM=1), V falling edge in a switching cycle. If this case happens for consecutive 256 switching cycles, the smart LDO reduces its output to 4.4V. If in any one of the 256 cycles, Vsw < 0 on LDrv falling edge, the counter is reset and LDO voltage doesn’t change. On the other hand, if Vsw < 0 on LDrv falling edge (DCM=0), LDO output is increased to 6.4V. A hysteresis band is added to Vsw comparison to avoid 21 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 ...
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Figure 12: Application Circuit for Simultaneous and Ratiometric Sequencing Tracking and sequencing operations can be implemented to be simultaneous or ratiometric (refer to Fig. 13 and 14). Figure 12 shows typical circuit configuration for sequencing operation. With this power‐up configuration, the voltage at the Vp pin of the slave reaches 0.5V before the Fb pin of the master. If R /R =R /R , simultaneous startup is achieved. That is, the output voltage of the slave follows that of the master until the voltage at the Vp pin of the slave reaches 0.5 V. After the voltage at the Vp pin of the slave exceeds 0.5V, the internal 0.5V reference of the slave dictates its output voltage. In reality the regulation gradually shifts from Vp to internal Vref. The circuit shown in Fig. 12 can also be used for simultaneous or ratiometric tracking operation if Vref of the slave is connected to GND. Table 2 summarizes the required conditions to achieve simultaneous/ratiometric tracking or sequencing operations. 22 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator ...
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VREF This pin reflects the internal reference voltage which is used by the error amplifier to set the output voltage. In most operating conditions this pin is only connected to an external bypass capacitor and it is left floating. A minimum 100pF ceramic capacitor is required from stability point of view. To keep stand by current to minimum, Vref is not allowed come up until EN starts going high. In tracking mode this pin should be pulled to GND. For margining applications, an external voltage source is connected to Vref pin and overrides the internal reference voltage. The external voltage source should have a low internal resistance (<100Ω) and be able to source and sink more than 25µA. POWER GOOD OUTPUT (TRACKING, SEQUENCING, VREF MARGINING) IR3894 continually monitors the output voltage via the sense pin (Vsns) voltage. The Vsns voltage is an input to the window comparator with upper and lower threshold of 0.6V and 0.45V respectively. PGood signal is high whenever Vsns voltage is within the PGood comparator window thresholds. The PGood pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. The threshold is set differently at different operating modes and the results of the comparison sets the PGood signal. Figures 15, 16, and 17 show the timing diagram of the PGood signal at different operating modes. Vsns signal is also used by OVP comparator for detecting output over voltage condition. Figure 15: Non‐sequence, Non‐tracking Startup and Vref Margin (Vp pin floating) 23 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator ...
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Figure 18: Timing Diagram for OVP in non‐tracking mode SOFT‐STOP (S_CTRL) Soft‐stop function can make output voltage discharge gradually. To enable this function, S_Ctrl is kept low first when EN goes high. Then S_Ctrl is pulled high to cross the logic level threshold (typical. 2V), the internal soft‐start ramp is initiated. So Vo follows Intl_SS to ramp up until it reaches its steady state. In soft‐stop process, S_Ctrl needs to be pulled low before EN goes low. After S_Ctrl goes below its threshold, a decreasing ramp is generated at Intl_SS with the same slope as in soft‐start ramp. Vo follows this ramp to discharge softly until shutdown completely. Figure 19 shows the timing diagram of S_Ctrl controlled soft‐start and soft‐stop. If the falling edge of Enable signal asserts before S_Ctrl falling edge, the converter is still turned off by Enable. Both gate drivers are turned off immediately and Vo discharges to zero. Figure 20 shows the timing diagram of Enable controlled soft‐start and soft‐stop. Soft stop feature also ensures that Vout discharges and also regulates the current precisely to zero with no undershoot. 24 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator Enable 0 S_Ctrl 0 0.65V Intl 0.15V _SS 0 Vout ...
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Any design or application using IR3894 must ensure operation with a pulse width that is higher than this minimum on‐time and preferably higher than 60 ns. This is necessary for the circuit to operate without jitter and pulse‐skipping, which can cause high inductor current ripple and high output voltage ripple. out t on In any application that uses IR3894, the following condition must be satisfied: (min t out on (min) V ...
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DESIGN EXAMPLE The following example is a typical application for IR3894. The application circuit is shown in Fig.28. Ripple Voltage= 1 Δ 50% load transient for = o ...
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When the control FET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage V . However, if the value of C1 is appropriately chosen, in the voltage V across C1 remains approximately c unchanged and the voltage at the Boot pin becomes: Boot Figure 24: Bootstrap circuit to generate Vc voltage A bootstrap capacitor of value 0.1uF is suitable for most applications. Input Capacitor Selection The ripple current generated during the on time of the control FET should be provided by the input capacitor. The RMS value of this ripple is expressed by: ...
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Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as: ESR ( ) o ESL ( ) ESR * o ESR ( ) ...
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F ESR 2 π* ESR ain ( ( ...
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V Z OUT REF Gain (dB) |H(s Figure 27: Type III Compensation network and its asymptotic gain plot Again, the transfer function is given by: ...
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The small signal value may be obtained from the manufacturer’s datasheets, design tools or spice models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency f and using equation (17) lc to compute the small signal These result to: F =24.9 kHz =5.3 MHz ESR F /2=300 kHz s Select crossover frequency F =100 kHz 0 Since F <F <Fs/2<F , Type III is selected to place the ESR pole and zeros. Detailed calculation of compensation Type III: Desired Phase Margin Θ = 70° 1 sin ...
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APPLICATION DIAGRAM Figure 28: Application Circuit for a 12V to 1.2V, 12A Point of Load Converter Suggested bill of materials for the application circuit Part Reference Qty Value SMD Electrolytic F size 25V 1 330uF Cin 1206, 25V, X5R, 20% 4 10uF 0.1uF 0603, 25V, X7R, 10% 0603, 25V, COG, 5% Cref 1 1nF C4 ...
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TYPICAL OPERATING WAVEFORMS PVin = 12V, Vo = 1.2V, Iout = 0‐12A, Room Temperature, No Air flow Figure 29: Start up at 12A Load, Ch :Vout, Ch :Vin, Good Figure 31: Start up with Pre Bias Voltage, 0A Load, Ch :V ...
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TYPICAL OPERATING WAVEFORMS Vin = 12V, Vo = 1.2V, Iout = 0‐12A, Room Temperature, No Air Flow Figure 35: Turn on at No Load showing Vcc level Ch1‐Vout, Ch2‐Vin,Ch3‐Vcc,Ch4‐Inductor current Figure 37: Transient Response, 6A to 12A step at 2.5A/uSec slew rate, 34 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator Figure 35: Turn on at No Load showing Vcc level Ch1‐Vout, Ch2‐Vin,Ch3‐Vcc,Ch4‐Inductor current ...
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TYPICAL OPERATING WAVEFORMS PVin = 12V, Vo = 1.2V, Iout = 0‐12A, Room Temperature, No Air flow Figure 38: Feed forward for Vin change from 6.8 to 16V, , Ch :V 1 out 4 in Figure 40: External frequency synchronization to 800kHz from free running 600kHz, o, voltage,Ch :SW Node voltage 3 ...
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TYPICAL OPERATING WAVEFORMS Vin = 12V, Vo = 1.2V, Iout = 0‐12A, Room Temperature, No Air Flow Figure 44: Bode Plot at 12A load shows a bandwidth of 99.9kHz and phase margin of 55.2° 36 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator Figure 45: Thermal Image of the Board at 12A Load, Test Point 1 is IR3894, Test Point 2 is inductor PD‐97745 IR3894 ...
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LAYOUT RECOMMENDATIONS The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the IR3899 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the PVin pin of IR3899. The feedback part of the system should be kept away from the inductor and other noise sources. Compensation parts should be placed as close as possible to the Comp pin ...
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Single point connection between AGND & PGND, should be close to the SupIRBuck kept away from noise sources Figure 46b: IRDC3894 Demo board Layout Considerations – Bottom Layer Analog ground plane Figure 46c: IRDC3894 Demo board Layout Considerations – Mid Layer 1 ...
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PCB METAL AND COMPONENT PLACEMENT Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self‐centering behavior is highly dependent on solders Figure 47: PCB Metal Pad Spacing (all dimensions in mm) * Contact International Rectifier to receive an electronic PCB Library file in your preferred format 39 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator and processes and experiments should be run to confirm the limits of self‐centering on specific processes. For further information, please refer to “SupIRBuck™ Multi‐Chip Module (MCM) Power Quad Flat No‐Lead (PQFN) Board Mounting Application Note.” (AN1132) PD‐97745 IR3894 ...
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SOLDER RESIST IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.) * Contact International Rectifier to receive an electronic PCB Library file in your preferred format 40 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined. When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment. Ensure that the solder resist in‐between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. Figure 48: Solder resist PD‐97745 IR3894 ...
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STENCIL DESIGN Stencils for PQFN can be used with thicknesses of 0.100‐0.250mm (0.004‐0.010"). Stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm‐0.200mm (0.005‐0.008"), with suitable reductions, give the best results. * Contact International Rectifier to receive an electronic PCB Library file in your preferred format 41 FEBRUARY 01, 2012 | DATA SHEET | Rev 3.0 12A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be adjusted for stencils of other thicknesses. Figure 49: Stencil Pad Spacing (all dimensions in mm) PD‐97745 IR3894 ...
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MARKING INFORMATION PACKAGE INFORMATION MILIMITERS DIM MIN MAX A 0.800 1.000 A1 0.000 0.050 b 0.375 0.475 b1 0.250 0.350 c 0.203 REF. D 5.000 BASIC E 6.000 BASIC e 1.033 BASIC e1 0.650 BASIC e2 0.852 BASIC ` IR WORLD HEADQUARTERS: ...