24LC65 Microchip Technology Inc., 24LC65 Datasheet

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24LC65

Manufacturer Part Number
24LC65
Description
Manufacturer
Microchip Technology Inc.
Datasheet

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FEATURES
• Voltage operating range: 2.5V to 6.0V
• Industry standard two wire bus protocol I
• 8 byte page, or byte modes available
• 2 ms typical write cycle time, byte or page
• 64-byte input cache for fast write loads
• Up to 8 devices may be connected to the same
• Including 100 kHz (2.5V) and 400 kHz (5.0V)
• Programmable block security options
• Programmable endurance options
• Schmitt trigger, filtered inputs for noise suppres-
• Output slope control to eliminate ground bounce
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Endurance:
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP/SOIC packages
• Temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24LC65 is a “smart” 8K
x 8 Serial Electrically Erasable PROM.
has been developed for advanced, low power applica-
tions such as personal communications, and provides
the systems designer with flexibility through the use of
many new user-programmable features. The 24LC65
offers a relocatable 4K bit block of ultra-high-endur-
ance memory for data that changes frequently. The
remainder of the array, or 60K bits, is rated at
1,000,000 ERASE/WRITE (E/W) cycles guaranteed.
The 24LC65 features an input cache for fast write loads
with a capacity of eight pages, or 64 bytes. This device
also features programmable security options for E/W
protection of critical data and/or code of up to fifteen 4K
I
Smart Serial is a trademark of Microchip Technology Inc.
2
C is a trademark of Philips Corporation.
1998 Microchip Technology Inc.
- Peak write current 3 mA at 6.0V
- Maximum read current 150 A at 6.0V
- Standby current 1 A typical
compatible
bus for up to 512K bits total memory
compatibility
sion
- 10,000,000 E/W cycles guaranteed for a High
- 1,000,000 E/W cycles guaranteed for a Stan-
- Commercial (C):
- Industrial (I)
Endurance Block
dard Endurance Block
64K 2.5V I
-40 C to +85 C
0 C to +70 C
2
C
2
This device
C
Smart Serial
PACKAGE TYPES
BLOCK DIAGRAM
blocks. Functional address lines allow the connection
of up to eight 24LC65's on the same bus for up to 512K
bits contiguous EEPROM memory. Advanced CMOS
technology makes this device ideal for low-power non-
volatile code and data applications. The 24LC65 is
available in the standard 8-pin plastic DIP and 8-pin
surface mount SOIC package.
SDA
PDIP
I/O
V
SOIC
V
CONTROL
CC
SS
LOGIC
I/O
SCL
V
A0
A1
A2
V
SS
A0
A0
A1
A2
SS
EEPROM
CONTROL
MEMORY
A1
LOGIC
A2
1
2
3
4
24LC65
1
2
3
4
XDEC
DS21073G-page 1
8
7
6
5
8
7
6
5
HV GENERATOR
PAGE LATCHES
R/W CONTROL
SENSE AMP
V
NC
SCL
SDA
EEPROM
ARRAY
CC
CACHE
YDEC
V
NC
SCL
SDA
CC

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24LC65 Summary of contents

Page 1

... blocks. Functional address lines allow the connection eight 24LC65's on the same bus for up to 512K bits contiguous EEPROM memory. Advanced CMOS technology makes this device ideal for low-power non- volatile code and data applications. The 24LC65 is available in the standard 8-pin plastic DIP and 8-pin surface mount SOIC package ...

Page 2

... ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* V ...................................................................................7.0V CC All inputs and outputs w.r.t. V ............... -0. Storage temperature ...................................... -65˚C to+150˚C Ambient temp. with power applied................. -65˚C to +125˚C Soldering temperature of leads (10 seconds) ............. +300˚C ESD protection on all pins *Notice: Stresses above those listed under “Maximum Ratings” ...

Page 3

... Schmitt trigger inputs which provide improved T HIGH DAT SU DAT 24LC65 Units Remarks kHz (Note 1) ns (Note 1) ns After this period the first clock pulse is generated ns Only relevant for repeated START condi- tion ...

Page 4

... NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24LC65) must leave the data line HIGH to enable the master to generate the STOP con- dition. ...

Page 5

... Upon receiving a 1010 code and appropriate device select bits, the slave device (24LC65) outputs an acknowledge signal on the SDA line. Depending upon the state of the R/W bit, the 24LC65 will select a read or write operation. Operation Control Code Device Select ...

Page 6

... FIGURE 4-2: PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 8- BUS CONTROL A ACTIVITY BYTE ADDRESS (1) R MASTER T S SDA LINE BUS C ACTIVITY: K FIGURE 4-3: CURRENT ADDRESS READ S T BUS ACTIVITY A MASTER R T SDA LINE S BUS ACTIVITY FIGURE 4-4: RANDOM READ S T CONTROL ...

Page 7

... To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LC65 as part of a write operation (R/W bit set to 0). After the word address is sent, the master generates a start condition following the acknowledge. This termi- nates the write operation, but not before the internal address pointer is set ...

Page 8

... Security Options The 24LC65 has a sophisticated mechanism for write-protecting portions of the array. This write protect function is programmable and allows the user to protect 0-15 contiguous 4K blocks. The user sets the security option by sending to the device the starting block num- ber for the protected region and the number of blocks to be protected. All parts will come from the factory in the default confi ...

Page 9

... PIN DESCRIPTIONS 8.1 A0, A1, A2 Chip Address Inputs The A0..A2 inputs are used by the 24LC65 for multiple device operation and conform to the two-wire bus stan- dard. The levels applied to these pins define the address block occupied by the device in the address map. A particular device is selected by transmitting the corresponding bits (A2, A1, A0) in the control byte (Figure 3-2 and Figure 8-1) ...

Page 10

... FIGURE 8-1: CONTROL SEQUENCE BIT ASSIGNMENTS Control Byte Address Byte R Slave Device Address Select Bits Security Read S t Acknowledges from Device ...

Page 11

... Page 0 of cache written to page 3 of array. Write cycle is executed after every page is written. byte 2 byte 3 byte 4 • • • byte 7 page 3 24LC65 cache page 7 • • • bytes 56-63 array row n • • • page 7 • • • page 7 array row beginning ...

Page 12

... NOTES: DS21073G-page 12 1998 Microchip Technology Inc. ...

Page 13

... NOTES: 1998 Microchip Technology Inc. 24LC65 DS21073G-page 13 ...

Page 14

... NOTES: DS21073G-page 14 1998 Microchip Technology Inc. ...

Page 15

... Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 24LC65 – /P Package: Temperature Range: Device: Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds ...

Page 16

... Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. ...

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